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Fix pbitcell array test

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mrg
2020-09-09 12:02:09 -07:00
parent 7bb21fb73f
commit 12fd60e8c3
1 changed files with 2 additions and 2 deletions
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compiler/tests/14_replica_pbitcell_array_test.py
+2 -2
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@@ -27,7 +27,7 @@ class replica_pbitcell_array_test(openram_test):
OPTS.num_w_ports = 0
debug.info(2, "Testing 4x4 array for pbitcell")
a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 1], add_rbl=[1, 1])
a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0], right_rbl=[1])
self.local_check(a)
OPTS.bitcell = "pbitcell"
@@ -39,7 +39,7 @@ class replica_pbitcell_array_test(openram_test):
factory.reset()
debug.info(2, "Testing 4x4 array for pbitcell")
a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 0], add_rbl=[1, 0])
a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 0], left_rbl=[0])
self.local_check(a)
globals.end_openram()