From 12fd60e8c3101b7ffb1b52674c695c94d73e8491 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 9 Sep 2020 12:02:09 -0700 Subject: [PATCH] Fix pbitcell array test --- compiler/tests/14_replica_pbitcell_array_test.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/tests/14_replica_pbitcell_array_test.py b/compiler/tests/14_replica_pbitcell_array_test.py index 8376241c..1cd2d9fc 100755 --- a/compiler/tests/14_replica_pbitcell_array_test.py +++ b/compiler/tests/14_replica_pbitcell_array_test.py @@ -27,7 +27,7 @@ class replica_pbitcell_array_test(openram_test): OPTS.num_w_ports = 0 debug.info(2, "Testing 4x4 array for pbitcell") - a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 1], add_rbl=[1, 1]) + a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0], right_rbl=[1]) self.local_check(a) OPTS.bitcell = "pbitcell" @@ -39,7 +39,7 @@ class replica_pbitcell_array_test(openram_test): factory.reset() debug.info(2, "Testing 4x4 array for pbitcell") - a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 0], add_rbl=[1, 0]) + a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 0], left_rbl=[0]) self.local_check(a) globals.end_openram()