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Cleanup unit test. Fix s_en control bug for r-only.

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This commit is contained in:
mrg
2019-07-16 13:51:31 -07:00
parent 2f55911604
commit 12fa36317e
4 changed files with 10 additions and 12 deletions
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compiler/modules/bank.py
+2 -2
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@@ -79,9 +79,9 @@ class bank(design.design):
for bit in range(self.word_size):
self.add_pin("dout{0}_{1}".format(port,bit),"OUT")
for port in self.read_ports:
self.add_pin(self.bitcell_array.get_rbl_bl_name(port),"OUT")
self.add_pin(self.bitcell_array.get_rbl_bl_name(self.port_rbl_map[port]),"OUT")
for port in self.read_ports:
self.add_pin(self.bitcell_array.get_rbl_wl_name(port),"IN")
self.add_pin(self.bitcell_array.get_rbl_wl_name(self.port_rbl_map[port]),"IN")
for port in self.write_ports:
for bit in range(self.word_size):
self.add_pin("din{0}_{1}".format(port,bit),"IN")
compiler/modules/control_logic.py
+1
View File
@@ -422,6 +422,7 @@ class control_logic(design.design):
if (self.port_type == "rw") or (self.port_type == "r") or self.words_per_row>1:
self.place_pen_row(row)
row += 1
if (self.port_type == "rw") or (self.port_type == "r"):
self.place_sen_row(row)
row += 1
self.place_delay(row)