mirror of https://github.com/VLSIDA/OpenRAM.git
Add partial grids as pins. Add previous paths as routing targets.
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@ -56,7 +56,7 @@ class router:
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self.blocked_grids = set()
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self.blocked_grids = set()
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# The corresponding set of partially blocked grids for each component.
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# The corresponding set of partially blocked grids for each component.
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# These are blockages for other nets but unblocked for this component.
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# These are blockages for other nets but unblocked for this component.
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self.pin_component_blockages = {}
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#self.pin_component_blockages = {}
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### The routed data structures
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### The routed data structures
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# A list of paths that have been "routed"
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# A list of paths that have been "routed"
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@ -233,8 +233,8 @@ class router:
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self.set_blockages(self.pin_components[name],True)
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self.set_blockages(self.pin_components[name],True)
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# Block all of the pin component partial blockages
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# Block all of the pin component partial blockages
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for name in self.pin_component_blockages.keys():
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#for name in self.pin_component_blockages.keys():
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self.set_blockages(self.pin_component_blockages[name],True)
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# self.set_blockages(self.pin_component_blockages[name],True)
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# These are the paths that have already been routed.
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# These are the paths that have already been routed.
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self.set_path_blockages()
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self.set_path_blockages()
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@ -732,10 +732,10 @@ class router:
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except:
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except:
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self.pin_components[pin_name] = []
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self.pin_components[pin_name] = []
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try:
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# try:
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self.pin_component_blockages[pin_name]
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# self.pin_component_blockages[pin_name]
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except:
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# except:
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self.pin_component_blockages[pin_name] = []
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# self.pin_component_blockages[pin_name] = []
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found_pin = False
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found_pin = False
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for pg in self.pin_groups[pin_name]:
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for pg in self.pin_groups[pin_name]:
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@ -759,13 +759,13 @@ class router:
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if (len(pin_set) == 0):
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if (len(pin_set) == 0):
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self.write_debug_gds()
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self.write_debug_gds()
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debug.error("Unable to find pin on grid.",-1)
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debug.error("Unable to find pin on grid.",-1)
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# We need to route each of the components, so don't combine the groups
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# We need to route each of the components, so don't combine the groups
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self.pin_components[pin_name].append(pin_set)
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self.pin_components[pin_name].append(pin_set | blockage_set)
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# Add all of the blocked grids to the set for the design
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# Add all of the blocked grids to the set for the design
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partial_set = blockage_set - pin_set
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#partial_set = blockage_set - pin_set
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self.pin_component_blockages[pin_name].append(partial_set)
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#self.pin_component_blockages[pin_name].append(partial_set)
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# Remove the blockage set from the blockages since these
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# Remove the blockage set from the blockages since these
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# will either be pins or partial pin blockges
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# will either be pins or partial pin blockges
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@ -826,8 +826,11 @@ class router:
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# FIXME: This could be optimized, but we just do a simple greedy biggest shape
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# FIXME: This could be optimized, but we just do a simple greedy biggest shape
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# for now.
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# for now.
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for pin_name in self.pin_components.keys():
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for pin_name in self.pin_components.keys():
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for pin_set,partial_set in zip(self.pin_components[pin_name],self.pin_component_blockages[pin_name]):
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#for pin_set,partial_set in zip(self.pin_components[pin_name],self.pin_component_blockages[pin_name]):
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total_pin_grids = pin_set | partial_set
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# total_pin_grids = pin_set | partial_set
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for pin_grids in self.pin_components[pin_name]:
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# Must duplicate so we don't destroy the original
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total_pin_grids=set(pin_grids)
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while self.enclose_pin_grids(total_pin_grids):
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while self.enclose_pin_grids(total_pin_grids):
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pass
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pass
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@ -867,6 +870,13 @@ class router:
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debug.info(1,"Set source: " + str(pin_name) + " " + str(pin_in_tracks))
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debug.info(1,"Set source: " + str(pin_name) + " " + str(pin_in_tracks))
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self.rg.add_source(pin_in_tracks)
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self.rg.add_source(pin_in_tracks)
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def add_path_target(self, paths):
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"""
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Set all of the paths as a target too.
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"""
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for p in paths:
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self.rg.set_target(p)
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self.rg.set_blocked(p,False)
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def add_pin_component_target(self, pin_name, index):
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def add_pin_component_target(self, pin_name, index):
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"""
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"""
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@ -209,7 +209,8 @@ class supply_router(router):
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num_components = self.num_pin_components(pin_name)
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num_components = self.num_pin_components(pin_name)
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debug.info(1,"Pin {0} has {1} components to route.".format(pin_name, num_components))
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debug.info(1,"Pin {0} has {1} components to route.".format(pin_name, num_components))
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recent_paths = []
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# For every component
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# For every component
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for index in range(num_components):
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for index in range(num_components):
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debug.info(2,"Routing component {0} {1}".format(pin_name, index))
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debug.info(2,"Routing component {0} {1}".format(pin_name, index))
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@ -225,11 +226,12 @@ class supply_router(router):
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# Add all of the rails as targets
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# Add all of the rails as targets
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# Don't add the other pins, but we could?
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# Don't add the other pins, but we could?
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self.add_supply_rail_target(pin_name)
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self.add_supply_rail_target(pin_name)
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# Actually run the A* router
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# Actually run the A* router
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if not self.run_router(detour_scale=5):
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if not self.run_router(detour_scale=5):
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self.write_debug_gds()
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self.write_debug_gds()
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recent_paths.append(self.paths[-1])
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@ -19,18 +19,19 @@ class no_blockages_test(openram_test):
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globals.init_openram("config_{0}".format(OPTS.tech_name))
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globals.init_openram("config_{0}".format(OPTS.tech_name))
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from supply_router import supply_router as router
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from supply_router import supply_router as router
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if True:
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if False:
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from control_logic import control_logic
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from control_logic import control_logic
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cell = control_logic(16)
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cell = control_logic(16)
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else:
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else:
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from sram import sram
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from sram import sram
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from sram_config import sram_config
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from sram_config import sram_config
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c = sram_config(word_size=4,
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c = sram_config(word_size=4,
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num_words=16,
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num_words=32,
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num_banks=1)
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num_banks=1)
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c.words_per_row=1
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c.words_per_row=1
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cell = sram(c, "sram1")
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sram = sram(c, "sram1")
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cell = sram.s
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layer_stack =("metal3","via3","metal4")
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layer_stack =("metal3","via3","metal4")
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rtr=router(layer_stack, cell)
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rtr=router(layer_stack, cell)
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