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Fixed issues with load capcitance units. Changed freepdk45 r and c wire values to be more in line with cacti.

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Hunter Nichols
2021-08-16 22:58:26 -07:00
parent b3500982ca
commit 12c03ddd9f
4 changed files with 9 additions and 16 deletions
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technology/freepdk45/tech/tech.py
+3 -3
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@@ -423,9 +423,9 @@ spice["temperatures"] = [0, 25, 100] # Temperature corners (celcius)
spice["nom_temperature"] = 25 # Nominal temperature (celcius)
# analytical delay parameters
spice["nom_threshold"] = 0.4 # Typical Threshold voltage in Volts
spice["wire_unit_r"] = 0.075 # Unit wire resistance in ohms/square
spice["wire_unit_c"] = 0.64e-12 # Unit wire capacitance F/um^2
spice["nom_threshold"] = 0.4 # Typical Threshold voltage in Volts
spice["wire_unit_r"] = 0.25 # Unit wire resistance in ohms/square
spice["wire_unit_c"] = 2.3e-16 # Unit wire capacitance F/um^2, calculated from CACTI 45dat
spice["min_tx_drain_c"] = 0.7 # Minimum transistor drain capacitance in ff
spice["min_tx_gate_c"] = 0.2 # Minimum transistor gate capacitance in ff
spice["dff_setup"] = 9 # DFF setup time in ps