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https://github.com/VLSIDA/OpenRAM.git
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Fixed issues with load capcitance units. Changed freepdk45 r and c wire values to be more in line with cacti.
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@@ -428,7 +428,7 @@ class spice():
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# Get wire values
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c_wire = self.module_wire_c()
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r_wire = self.module_wire_r()
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# Calculate tau with provided output load then calc delay
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tf = rd*(c_intrinsic+c_load+c_wire)+r_wire*(c_load+c_wire/2)
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this_delay = self.horowitz(inrisetime, tf, 0.5, 0.5, True)
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inrisetime = this_delay / (1.0 - 0.5)
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@@ -115,10 +115,7 @@ class timing_graph():
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else:
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debug.error("Undefined model_name for analytical timing: {}".format(params["model_name"]),
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return_value=1)
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#cout+=output_edge_mod.get_cin() # logical effort based CIN
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#cout+=output_edge_mod.get_input_capacitance() #cacti called from module
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#func = cacti_params["cin_function"]
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#cout+=output_edge_mod.func()
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# If at the last output, include the final output load
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if i == len(path) - 2:
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cout += load
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@@ -130,10 +127,6 @@ class timing_graph():
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else:
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debug.error("Undefined model_name for analytical timing: {}".format(params["model_name"]),
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return_value=1)
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#delays.append(path_edge_mod.analytical_delay(corner, cur_slew, cout))
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#delays.append(path_edge_mod.cacti_delay(corner, cur_slew, cout, cacti_params))
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#delays.append(path_edge_mod.cacti_params["delay_function"](corner, cur_slew, cout, cacti_params))
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cur_slew = delays[-1].slew
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return delays
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@@ -72,14 +72,14 @@ class cacti(simulation):
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for load,slew in load_slews:
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# Calculate delay based on slew and load
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# Calculations expect Farad, input is Femto-Farad
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load_farad = load*1e-12
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load_farad = 0.052275e-12
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load_farad = load*1e-15
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#load_farad = 0.052275e-12
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slew = 0
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path_delays = self.graph.get_timing(bl_path, self.corner, slew, load_farad, self.params)
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total_delay = self.sum_delays(path_delays)
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debug.info(0, "total_delay={}".format(total_delay))
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sys.exit()
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#debug.info(0, "total_delay={}".format(total_delay))
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#sys.exit()
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delay_ns = total_delay.delay/1e-9
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slew_ns = total_delay.slew/1e-9
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max_delay = max(max_delay, total_delay.delay)
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