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Added SA parameters for CACTI delay. Fixed syntax issues in several modules. Fixed issue with slew not being propogated to the next delay stage.

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Hunter Nichols
2021-09-07 15:56:27 -07:00
parent 6b8d143073
commit 1236a0773a
7 changed files with 19 additions and 15 deletions
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technology/freepdk45/tech/tech.py
+3 -1
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@@ -470,7 +470,9 @@ spice["c_junc"] = 5e-16 #F/um^2
spice["c_junc_sw"] = 5e-16 #F/um
spice["wire_c_per_um"] = spice["wire_unit_c"]*drc["minwidth_m2"] # Unit c by m2 width, F/um units
spice["wire_r_per_um"] = spice["wire_unit_r"]/drc["minwidth_m2"] # Unit r per m2 width, Ohms/um units
spice["mobility_n"] = 0.045e8 # um^2/(V*s)
spice["V_dsat"] = 0.0938 # From CACTI 45nm tech
spice["sa_transconductance"] = (spice["mobility_n"])*spice["cox"]*(parameter["sa_inv_nmos_size"]/_lambda_)*spice["V_dsat"]
###################################################
# Technology Tool Preferences
###################################################
technology/scn4m_subm/tech/tech.py
+4
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@@ -416,6 +416,10 @@ spice["c_junc"] = 9.276962e-16 #F/um^2
spice["c_junc_sw"] = 3.181055e-16 #F/um
spice["wire_c_per_um"] = spice["wire_unit_c"]*drc["minwidth_m2"] # Unit c by m2 width, F/um units
spice["wire_r_per_um"] = spice["wire_unit_r"]/drc["minwidth_m2"] # Unit r per m2 width, Ohms/um units
spice["mobility_n"] = 444.94e8 # um^2/(V*s)
spice["V_dsat"] = 0.256 # From CACTI 180nm tech
spice["sa_transconductance"] = (spice["mobility_n"])*spice["cox"]*(parameter["sa_inv_nmos_size"]/_lambda_)*spice["V_dsat"]
###################################################
# Technology Tool Preferences