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https://github.com/VLSIDA/OpenRAM.git
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check delay chain pinout list, add cs_buf to control logic
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@@ -21,7 +21,7 @@ class multi_delay_chain(design.design):
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Supplying an empty pinout list will result in an output on the last stage.
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"""
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def __init__(self, name, fanout_list, pinout_list):
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def __init__(self, name, fanout_list, pinout_list = None):
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"""init function"""
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super().__init__(name)
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debug.info(1, "creating delay chain {0}".format(str(fanout_list)))
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@@ -36,10 +36,17 @@ class multi_delay_chain(design.design):
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self.rows = len(self.fanout_list)
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# defaults to signle output at end of delay chain
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if len(pinout_list) == 0:
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if not pinout_list:
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self.pinout_list = [self.rows] # TODO: check for off-by-one here
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else:
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self.pinout_list = pinout_list
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# Set() to sort in ascending order and remove duplicates
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self.pinout_list = set(pinout_list)
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# Check pinout bounds
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debug.check(self.pinout_list[-1] <= self.rows,
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"Ouput pin cannot exceed delay chain length.")
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debug.check(self.pinout_list[0] > 0,
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"Delay chain output pin numbers must be positive")
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self.create_netlist()
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if not OPTS.netlist_only:
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