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check delay chain pinout list, add cs_buf to control logic

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samuelkcrow
2022-07-21 19:35:01 -07:00
parent 78013d32b7
commit 11ea82e782
2 changed files with 18 additions and 4 deletions
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compiler/modules/control_logic_delay.py
+8 -1
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@@ -297,6 +297,7 @@ class control_logic_delay(design.design):
""" Create all the instances """
self.create_dffs()
self.create_clk_buf_row()
self.create_cs_buf_row()
self.create_gated_clk_bar_row()
self.create_gated_clk_buf_row()
self.create_delay()
@@ -443,6 +444,12 @@ class control_logic_delay(design.design):
mod=self.clk_buf_driver)
self.connect_inst(["clk", "clk_buf", "vdd", "gnd"])
def create_clk_buf_row(self):
""" Create the multistage and gated chip select buffer """
self.cs_buf_inst = self.add_inst(name="csbuf",
mod=self.clk_buf_driver)
self.connect_inst(["cs", "cs_buf", "vdd", "gnd"])
def place_clk_buf_row(self, row):
x_offset = self.control_x_offset
@@ -543,7 +550,7 @@ class control_logic_delay(design.design):
def create_wlen_row(self):
self.wl_en_unbuf_and_inst = self.add_inst(name="and_wl_en_unbuf",
mod=self.wl_en_and)
self.connect_inst(["cs", "glitch2_bar", "wl_en_unbuf", "vdd", "gnd"])
self.connect_inst(["cs_buf", "glitch2_bar", "wl_en_unbuf", "vdd", "gnd"])
self.wl_en_inst=self.add_inst(name="buf_wl_en",
mod=self.wl_en_driver)