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change bitline names to bl br for single port

This commit is contained in:
jcirimel 2020-10-20 03:15:34 -07:00
parent 6a1f12b62d
commit 118b2b1215
1 changed files with 2 additions and 2 deletions
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4
compiler/base/custom_cell_properties.py
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@ -43,8 +43,8 @@ class _bitcell:
def _default(): def _default():
axis = _mirror_axis(True, False) axis = _mirror_axis(True, False)
cell_s8_6t = _cell({'bl' : 'bl0', cell_s8_6t = _cell({'bl' : 'bl',
'br' : 'bl1', 'br' : 'br',
'wl': 'wl'}) 'wl': 'wl'})
cell_6t = _cell({'bl' : 'bl', cell_6t = _cell({'bl' : 'bl',