From 118b2b1215a8f7ae35b62c3d318c9d7dc470abff Mon Sep 17 00:00:00 2001
From: jcirimel <jcirimel@ucsc.edu>
Date: Tue, 20 Oct 2020 03:15:34 -0700
Subject: [PATCH] change bitline names to bl br for single port

---
 compiler/base/custom_cell_properties.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/compiler/base/custom_cell_properties.py b/compiler/base/custom_cell_properties.py
index 2e21c1ec..e02ffbe8 100644
--- a/compiler/base/custom_cell_properties.py
+++ b/compiler/base/custom_cell_properties.py
@@ -43,8 +43,8 @@ class _bitcell:
     def _default():
         axis = _mirror_axis(True, False)
 
-        cell_s8_6t = _cell({'bl' : 'bl0',
-                            'br' : 'bl1',
+        cell_s8_6t = _cell({'bl' : 'bl',
+                            'br' : 'br',
                             'wl': 'wl'})
 
         cell_6t = _cell({'bl' : 'bl',