change bitline names to bl br for single port

2020-10-20 03:15:34 -07:00 · 2020-10-20 03:15:34 -07:00 · 118b2b1215
parent 6a1f12b62d
commit 118b2b1215
1 changed files with 2 additions and 2 deletions
--- a/compiler/base/custom_cell_properties.py
+++ b/compiler/base/custom_cell_properties.py
@ -43,8 +43,8 @@ class _bitcell:
    def _default():
        axis = _mirror_axis(True, False)

-        cell_s8_6t = _cell({'bl' : 'bl0',
-                            'br' : 'bl1',
+        cell_s8_6t = _cell({'bl' : 'bl',
+                            'br' : 'br',
                            'wl': 'wl'})

        cell_6t = _cell({'bl' : 'bl',