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Enable riscv tests

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This commit is contained in:
Matt Guthaus
2020-09-30 12:39:40 -07:00
parent f4e6a8895b
commit 112d57d90a
7 changed files with 47 additions and 53 deletions
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compiler/modules/bank.py
+4 -5
View File
@@ -8,8 +8,8 @@
import debug
import design
from sram_factory import factory
from math import log, ceil, floor, sqrt
from tech import drc
from math import log, ceil, floor
from tech import drc, layer
from vector import vector
from globals import OPTS
@@ -374,8 +374,6 @@ class bank(design.design):
port=port))
self.add_mod(self.port_address[port])
total_cols = self.num_cols + self.num_spare_cols
try:
local_array_size = OPTS.local_array_size
except AttributeError:
@@ -383,6 +381,7 @@ class bank(design.design):
if local_array_size > 0:
# Find the even multiple that satisfies the fanout with equal sized local arrays
total_cols = self.num_cols + self.num_spare_cols
num_lb = floor(total_cols / local_array_size)
final_size = total_cols - num_lb * local_array_size
cols = [local_array_size] * (num_lb - 1)
@@ -393,7 +392,7 @@ class bank(design.design):
rows=self.num_rows)
else:
self.bitcell_array = factory.create(module_type="replica_bitcell_array",
cols=total_cols,
cols=self.num_cols + self.num_spare_cols,
rows=self.num_rows)
self.add_mod(self.bitcell_array)
compiler/modules/write_driver_array.py
+13 -11
View File
@@ -215,25 +215,27 @@ class write_driver_array(design.design):
start_layer=pin.layer)
if self.write_size:
for bit in range(self.num_wmasks):
first_inst = self.driver_insts[bit * self.write_size]
first_en_pin = first_inst.get_pin(first_inst.mod.en_name)
inst = self.driver_insts[bit * self.write_size]
en_pin = inst.get_pin(inst.mod.en_name)
# Determine width of wmask modified en_pin with/without col mux
wmask_en_len = self.words_per_row * (self.write_size * self.driver_spacing)
if (self.words_per_row == 1):
en_gap = self.driver_spacing - en_pin.width()
else:
en_gap = self.driver_spacing
last_inst = self.driver_insts[(bit + 1) * self.write_size - 1]
last_en_pin = last_inst.get_pin(last_inst.mod.en_name)
wmask_en_len = last_en_pin.rx() - first_en_pin.lx()
self.add_layout_pin(text=self.en_name + "_{0}".format(bit),
layer=first_en_pin.layer,
offset=first_en_pin.ll(),
width=wmask_en_len,
height=first_en_pin.height())
layer=en_pin.layer,
offset=en_pin.ll(),
width=wmask_en_len - en_gap,
height=en_pin.height())
for i in range(self.num_spare_cols):
inst = self.driver_insts[self.word_size + i]
en_pin = inst.get_pin(inst.mod.en_name)
self.add_layout_pin(text=self.en_name + "_{0}".format(i + self.num_wmasks),
layer="m1",
offset=en_pin.lr() + vector(-drc("minwidth_m1"), 0))
offset=en_pin.lr() + vector(-drc("minwidth_m1"),0))
elif self.num_spare_cols and not self.write_size:
# shorten enable rail to accomodate those for spare write drivers