From 10753a0802671de9e7597911420fb6bc38917a9e Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 16 Sep 2021 15:42:02 -0700 Subject: [PATCH] Change via2 to 65nm to be compatible with Calibre FreePDK45 deck --- technology/freepdk45/tech/freepdk45.lydrc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/technology/freepdk45/tech/freepdk45.lydrc b/technology/freepdk45/tech/freepdk45.lydrc index 1d719e33..91c7c30f 100644 --- a/technology/freepdk45/tech/freepdk45.lydrc +++ b/technology/freepdk45/tech/freepdk45.lydrc @@ -199,7 +199,8 @@ metal2_gt1500.edges.with_length(4.um,nil).space(1500.nm,euclidian).output("METAL [ metal2_gt90, metal2_gt270, metal2_gt500, metal2_gt900, metal2_gt1500 ].each { |l| l.forget } # via2 -via2.edges.without_length(70.nm).output("VIA2.1", "VIA2.1 : Minimum/Maximum width of via2 : 70nm") +# FreePDK Calibre deck incorrectly has this as 65nm so we are going to be compatible. +via2.edges.without_length(65.nm).output("VIA2.1", "VIA2.1 : Minimum/Maximum width of via2 : 65nm") via2.space(85.nm, euclidian).output("VIA2.2", "VIA2.2 : Minimum spacing of via2 : 85nm") via2.not(metal2).output("VIA2.3", "VIA2.3 : via2 must be inside metal2") via2.not(metal3).output("VIA2.4", "VIA2.4 : via2 must be inside metal3")