mirror of https://github.com/VLSIDA/OpenRAM.git
begin fixes to pbitcell, prepare multibank pex
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parent
40c01dab85
commit
1062cbfd7f
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@ -321,7 +321,7 @@ class instance(geometry):
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cell_paths.append(copy.copy(path))
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cell_paths.append(copy.copy(path))
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normalized_storage_nets = node.mod.get_normalized_storage_nets_offset()
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normalized_storage_nets = node.mod.get_normalized_storage_nets_offset()
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normalized_bitline_nets = node.mod.get_normalized_bitline_offset()
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(normalized_bl_offsets, normalized_br_offsets) = node.mod.get_normalized_bitline_offset()
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Q_x = normalized_storage_nets[0][0]
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Q_x = normalized_storage_nets[0][0]
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Q_y = normalized_storage_nets[0][1]
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Q_y = normalized_storage_nets[0][1]
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@ -329,22 +329,26 @@ class instance(geometry):
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Q_bar_x = normalized_storage_nets[1][0]
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Q_bar_x = normalized_storage_nets[1][0]
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Q_bar_y = normalized_storage_nets[1][1]
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Q_bar_y = normalized_storage_nets[1][1]
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bl_x = normalized_bitline_nets[0][0]
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bl_y = normalized_bitline_nets[0][1]
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br_x = normalized_bitline_nets[1][0]
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br_y = normalized_bitline_nets[1][1]
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if node.mirror == 'MX':
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if node.mirror == 'MX':
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Q_y = -1 * Q_y
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Q_y = -1 * Q_y
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Q_bar_y = -1 * Q_bar_y
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Q_bar_y = -1 * Q_bar_y
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bl_y = -1 * bl_y
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for pair in range(len(normalized_bl_offsets)):
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br_y = -1 * br_y
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for offset in range(len(offset)):
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normalized_bl_offsets[pair][offset] = -1 * normalized_bl_offsets[pair][offset]
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for pair in range(len(normalized_br_offsets)):
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for offset in range(len(offset)):
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normalized_br_offsets[pair][offset] = -1 * normalized_br_offsets[pair][offset]
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Q_offsets.append([Q_x, Q_y])
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Q_offsets.append([Q_x, Q_y])
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Q_bar_offsets.append([Q_bar_x, Q_bar_y])
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Q_bar_offsets.append([Q_bar_x, Q_bar_y])
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bl_offsets.append([bl_x, bl_y])
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br_offsets.append([br_x, br_y])
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for offset in bl_offset:
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bl_offsets.append(offset)
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for offset in br.offset:
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br_offsets.append(offset)
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elif node.mod.insts is not []:
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elif node.mod.insts is not []:
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for instance in node.mod.insts:
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for instance in node.mod.insts:
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@ -100,21 +100,39 @@ class bitcell_base(design.design):
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return(self.storage_net_offsets)
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return(self.storage_net_offsets)
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def get_bitline_offset(self):
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def get_bitline_offset(self):
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self.bitline_names = ["bl", "br"]
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found_bitlines = []
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bl_names = self.get_all_bl_names()
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self.bitline_offsets = []
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br_names = self.get_all_br_names()
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for i in range(len(self.bitline_names)):
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found_bl = []
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found_br = []
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self.bl_offsets = []
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self.br_offsets = []
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for i in range(len(bl_names)):
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for text in self.gds.getTexts(layer["metal2"]):
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for text in self.gds.getTexts(layer["metal2"]):
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if not self.bitline_names[i] in found_bitlines:
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if not bl_names[i] in found_bl:
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if self.bitline_names[i] == text.textString.rstrip('\x00'):
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if bl_names[i] == text.textString.rstrip('\x00'):
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self.bitline_offsets.append(text.coordinates[0])
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self.bl_offsets.append(text.coordinates[0])
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found_bitlines.append(self.bitline_names[i])
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found_bl.append(bl_names[i])
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continue
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continue
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for i in range(len(self.bitline_offsets)):
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for i in range(len(br_names)):
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self.bitline_offsets[i] = tuple([self.gds.info["units"][0] * x for x in self.bitline_offsets[i]])
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for text in self.gds.getTexts(layer["metal2"]):
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if not br_names[i] in found_br:
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if br_names[i] == text.textString.rstrip('\x00'):
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self.br_offsets.append(text.coordinates[0])
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found_br.append(br_names[i])
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continue
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return(self.bitline_offsets)
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for i in range(len(self.bl_offsets)):
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self.bl_offsets[i] = tuple([self.gds.info["units"][0] * x for x in self.bl_offsets[i]])
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for i in range(len(self.br_offsets)):
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self.br_offsets[i] = tuple([self.gds.info["units"][0] * x for x in self.br_offsets[i]])
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return(self.bl_offsets, self.br_offsets)
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def get_normalized_storage_nets_offset(self):
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def get_normalized_storage_nets_offset(self):
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"""
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"""
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@ -105,22 +105,30 @@ class sram_base(design, verilog, lef):
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storage_layer_name = "metal1"
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storage_layer_name = "metal1"
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bitline_layer_name = "metal2"
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bitline_layer_name = "metal2"
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for i in range(0,len(bank_offset)):
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Q = [bank_offset[bank_num][0] + Q_offset[bank_num][0], bank_offset[bank_num][1] + Q_offset[bank_num][1]]
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Q_bar = [bank_offset[bank_num][0] + Q_bar_offset[bank_num][0], bank_offset[bank_num][1] + Q_bar_offset[bank_num][1]]
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Q = [bank_offset[i][0] + Q_offset[i][0], bank_offset[i][1] + Q_offset[i][1]]
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bl = []
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Q_bar = [bank_offset[i][0] + Q_bar_offset[i][0], bank_offset[i][1] + Q_bar_offset[i][1]]
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br = []
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bl = [bank_offset[i][0] + bl_offsets[i][0], bank_offset[i][1] + bl_offsets[i][1]]
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br = [bank_offset[i][0] + br_offsets[i][0], bank_offset[i][1] + br_offsets[i][1]]
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self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , storage_layer_name, Q)
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for i in range(len(bl_offsets)):
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self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), storage_layer_name, Q_bar)
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bl.append([bank_offset[bank_num][1] + bl_offsets[bank_num][2*(i)], bank_offset[bank_num][1] + bl_offsets[bank_num][2*(i)+1]])
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if OPTS.num_banks == 1:
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for i in range(len(br_offsets)):
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br.append([bank_offset[bank_num][1] + br_offsets[bank_num][2*(i)], bank_offset[bank_num][1] + br_offsets[bank_num][2*(i)+1]])
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self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , storage_layer_name, Q)
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self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), storage_layer_name, Q_bar)
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if OPTS.num_banks == 1:
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for i in range(len(bl_offsets)):
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self.add_layout_pin_rect_center("bl_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, bl)
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self.add_layout_pin_rect_center("bl_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, bl)
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for i in range(len(br_offsets)):
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self.add_layout_pin_rect_center("br_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), bitline_layer_name, br)
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self.add_layout_pin_rect_center("br_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), bitline_layer_name, br)
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else:
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else:
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self.add_layout_pin_rect_center("bl{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, bl)
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self.add_layout_pin_rect_center("bl{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, bl)
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self.add_layout_pin_rect_center("br{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), bitline_layer_name, br)
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self.add_layout_pin_rect_center("br{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), bitline_layer_name, br)
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@ -178,8 +186,8 @@ class sram_base(design, verilog, lef):
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highest_coord = self.find_highest_coords()
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highest_coord = self.find_highest_coords()
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self.width = highest_coord[0]
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self.width = highest_coord[0]
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self.height = highest_coord[1]
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self.height = highest_coord[1]
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if OPTS.use_pex:
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self.add_global_pex_labels()
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self.add_global_pex_labels()
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start_time = datetime.now()
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start_time = datetime.now()
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# We only enable final verification if we have routed the design
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# We only enable final verification if we have routed the design
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