mirror of https://github.com/VLSIDA/OpenRAM.git
Fixed test 23_sram_prune test. Fixed syntax errors in golden lib files.
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bf34911f3f
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@ -87,16 +87,16 @@ cell (sram_2_16_1_freepdk45){
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cell_leakage_power : 0;
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bus(DIN){
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bus_type : DATA;
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direction : in;
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max_capacitance : 1.6728;
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min_capacitance : 0.052275;
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direction : input;
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capacitance : 0.2091;
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memory_write(){
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address : ADDR;
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clocked_on : clk;
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}
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}
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bus(DOUT){
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bus_type : DATA;
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direction : out;
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direction : output;
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max_capacitance : 1.6728;
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min_capacitance : 0.052275;
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memory_read(){
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@ -229,39 +229,6 @@ cell (sram_2_16_1_freepdk45){
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}
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}
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pin(OEb){
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direction : input;
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capacitance : 0.2091;
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timing(){
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timing_type : setup_rising;
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related_pin : "clk";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.015, 0.027",\
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"0.009, 0.015, 0.027",\
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"0.009, 0.015, 0.027");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.009, 0.015",\
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"0.009, 0.009, 0.015",\
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"0.009, 0.009, 0.015");
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}
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}
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timing(){
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timing_type : hold_rising;
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related_pin : "clk";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.002, 0.002, -0.004",\
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"0.002, 0.002, -0.004",\
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"0.002, 0.002, -0.004");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("-0.004, -0.004, -0.016",\
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"-0.004, -0.004, -0.016",\
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"-0.004, -0.004, -0.016");
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}
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}
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}
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pin(WEb){
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direction : input;
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capacitance : 0.2091;
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@ -87,16 +87,16 @@ cell (sram_2_16_1_scn3me_subm){
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cell_leakage_power : 0;
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bus(DIN){
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bus_type : DATA;
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direction : in;
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max_capacitance : 78.5936;
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min_capacitance : 2.45605;
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direction : input;
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capacitance : 9.8242;
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memory_write(){
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address : ADDR;
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clocked_on : clk;
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}
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}
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bus(DOUT){
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bus_type : DATA;
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direction : out;
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direction : output;
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max_capacitance : 78.5936;
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min_capacitance : 2.45605;
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memory_read(){
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@ -229,39 +229,6 @@ cell (sram_2_16_1_scn3me_subm){
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}
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}
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pin(OEb){
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direction : input;
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capacitance : 9.8242;
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timing(){
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timing_type : setup_rising;
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related_pin : "clk";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.076, 0.076, 0.149",\
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"0.076, 0.076, 0.149",\
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"0.076, 0.076, 0.149");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.033, 0.039, 0.027",\
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"0.033, 0.039, 0.027",\
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"0.033, 0.039, 0.027");
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}
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}
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timing(){
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timing_type : hold_rising;
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related_pin : "clk";
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rise_constraint(CONSTRAINT_TABLE) {
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values("-0.004, -0.004, 0.009",\
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"-0.004, -0.004, 0.009",\
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"-0.004, -0.004, 0.009");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("-0.052, -0.059, -0.132",\
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"-0.052, -0.059, -0.132",\
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"-0.052, -0.059, -0.132");
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}
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}
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}
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pin(WEb){
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direction : input;
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capacitance : 9.8242;
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@ -183,9 +183,9 @@ class openram_test(unittest.TestCase):
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# 4. Check if remaining string matches
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if line1 != line2:
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#Uncomment if you want to see all the chars of the two lines separated
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#print(str([i for i in line1]))
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#print(str([i for i in line2]))
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#Uncomment if you want to see all the individual chars of the two lines
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print(str([i for i in line1]))
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print(str([i for i in line2]))
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if mismatches==0:
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debug.error("Mismatching files:\nfile1={0}\nfile2={1}".format(filename1,filename2))
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mismatches += 1
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