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Fixed test 23_sram_prune test. Fixed syntax errors in golden lib files.

This commit is contained in:
Hunter Nichols 2018-09-06 22:06:23 -07:00
parent bf34911f3f
commit 0ff3b29b66
3 changed files with 11 additions and 77 deletions
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41
compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib
View File

@ -87,16 +87,16 @@ cell (sram_2_16_1_freepdk45){
cell_leakage_power : 0; cell_leakage_power : 0;
bus(DIN){ bus(DIN){
bus_type : DATA; bus_type : DATA;
direction : in; direction : input;
max_capacitance : 1.6728; capacitance : 0.2091;
min_capacitance : 0.052275;
memory_write(){ memory_write(){
address : ADDR; address : ADDR;
clocked_on : clk; clocked_on : clk;
} }
}
bus(DOUT){ bus(DOUT){
bus_type : DATA; bus_type : DATA;
direction : out; direction : output;
max_capacitance : 1.6728; max_capacitance : 1.6728;
min_capacitance : 0.052275; min_capacitance : 0.052275;
memory_read(){ memory_read(){
@ -229,39 +229,6 @@ cell (sram_2_16_1_freepdk45){
} }
} }
pin(OEb){
direction : input;
capacitance : 0.2091;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.027",\
"0.009, 0.015, 0.027",\
"0.009, 0.015, 0.027");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015",\
"0.009, 0.009, 0.015");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004",\
"0.002, 0.002, -0.004");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016",\
"-0.004, -0.004, -0.016");
}
}
}
pin(WEb){ pin(WEb){
direction : input; direction : input;
capacitance : 0.2091; capacitance : 0.2091;

41
compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_pruned.lib
View File

@ -87,16 +87,16 @@ cell (sram_2_16_1_scn3me_subm){
cell_leakage_power : 0; cell_leakage_power : 0;
bus(DIN){ bus(DIN){
bus_type : DATA; bus_type : DATA;
direction : in; direction : input;
max_capacitance : 78.5936; capacitance : 9.8242;
min_capacitance : 2.45605;
memory_write(){ memory_write(){
address : ADDR; address : ADDR;
clocked_on : clk; clocked_on : clk;
} }
}
bus(DOUT){ bus(DOUT){
bus_type : DATA; bus_type : DATA;
direction : out; direction : output;
max_capacitance : 78.5936; max_capacitance : 78.5936;
min_capacitance : 2.45605; min_capacitance : 2.45605;
memory_read(){ memory_read(){
@ -229,39 +229,6 @@ cell (sram_2_16_1_scn3me_subm){
} }
} }
pin(OEb){
direction : input;
capacitance : 9.8242;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.076, 0.076, 0.149",\
"0.076, 0.076, 0.149",\
"0.076, 0.076, 0.149");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.033, 0.039, 0.027",\
"0.033, 0.039, 0.027",\
"0.033, 0.039, 0.027");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("-0.004, -0.004, 0.009",\
"-0.004, -0.004, 0.009",\
"-0.004, -0.004, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.052, -0.059, -0.132",\
"-0.052, -0.059, -0.132",\
"-0.052, -0.059, -0.132");
}
}
}
pin(WEb){ pin(WEb){
direction : input; direction : input;
capacitance : 9.8242; capacitance : 9.8242;

6
compiler/tests/testutils.py
View File

@ -183,9 +183,9 @@ class openram_test(unittest.TestCase):
# 4. Check if remaining string matches # 4. Check if remaining string matches
if line1 != line2: if line1 != line2:
#Uncomment if you want to see all the chars of the two lines separated #Uncomment if you want to see all the individual chars of the two lines
#print(str([i for i in line1])) print(str([i for i in line1]))
#print(str([i for i in line2])) print(str([i for i in line2]))
if mismatches==0: if mismatches==0:
debug.error("Mismatching files:\nfile1={0}\nfile2={1}".format(filename1,filename2)) debug.error("Mismatching files:\nfile1={0}\nfile2={1}".format(filename1,filename2))
mismatches += 1 mismatches += 1