diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py
index 8ecc115e..4a813269 100644
--- a/compiler/pgates/pnand2.py
+++ b/compiler/pgates/pnand2.py
@@ -66,13 +66,23 @@ class pnand2(pgate.pgate):
 
     def add_ptx(self):
         """ Create the PMOS and NMOS transistors. """
-        self.nmos = factory.create(module_type="ptx",
-                                   width=self.nmos_width,
-                                   mults=self.tx_mults,
-                                   tx_type="nmos",
-                                   connect_poly=True,
-                                   connect_active=True)
-        self.add_mod(self.nmos)
+        self.nmos_nd = factory.create(module_type="ptx",
+                                      width=self.nmos_width,
+                                      mults=self.tx_mults,
+                                      tx_type="nmos",
+                                      add_drain_contact=False,
+                                      connect_poly=True,
+                                      connect_active=True)
+        self.add_mod(self.nmos_nd)
+        
+        self.nmos_ns = factory.create(module_type="ptx",
+                                      width=self.nmos_width,
+                                      mults=self.tx_mults,
+                                      tx_type="nmos",
+                                      add_source_contact=False,
+                                      connect_poly=True,
+                                      connect_active=True)
+        self.add_mod(self.nmos_ns)
 
         self.pmos = factory.create(module_type="ptx",
                                    width=self.pmos_width,
@@ -99,9 +109,9 @@ class pnand2(pgate.pgate):
 
         # This is the extra space needed to ensure DRC rules
         # to the active contacts
-        extra_contact_space = max(-self.nmos.get_pin("D").by(), 0)
+        extra_contact_space = max(-self.nmos_nd.get_pin("D").by(), 0)
         # This is a poly-to-poly of a flipped cell
-        self.top_bottom_space = max(0.5 * self.m1_width + self.m1_space + extra_contact_space, 
+        self.top_bottom_space = max(0.5 * self.m1_width + self.m1_space + extra_contact_space,
                                     self.poly_extend_active + self.poly_space)
         
     def route_supply_rails(self):
@@ -130,11 +140,11 @@ class pnand2(pgate.pgate):
         self.connect_inst(["Z", "B", "vdd", "vdd"])
 
         self.nmos1_inst = self.add_inst(name="pnand2_nmos1",
-                                        mod=self.nmos)
+                                        mod=self.nmos_nd)
         self.connect_inst(["Z", "B", "net1", "gnd"])
 
         self.nmos2_inst = self.add_inst(name="pnand2_nmos2",
-                                        mod=self.nmos)
+                                        mod=self.nmos_ns)
         self.connect_inst(["net1", "A", "gnd", "gnd"])
 
     def place_ptx(self):
@@ -160,7 +170,7 @@ class pnand2(pgate.pgate):
 
         # Output position will be in between the PMOS and NMOS
         self.output_pos = vector(0,
-                                 0.5 * (pmos1_pos.y + nmos1_pos.y + self.nmos.active_height))
+                                 0.5 * (pmos1_pos.y + nmos1_pos.y + self.nmos_nd.active_height))
 
     def add_well_contacts(self):
         """ 
@@ -169,7 +179,7 @@ class pnand2(pgate.pgate):
         """
 
         self.add_nwell_contact(self.pmos, self.pmos2_pos)
-        self.add_pwell_contact(self.nmos, self.nmos2_pos)
+        self.add_pwell_contact(self.nmos_nd, self.nmos2_pos)
         
     def connect_rails(self):
         """ Connect the nmos and pmos to its respective power rails """