diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py
index 44318206..03b787f4 100644
--- a/compiler/modules/bitcell_array.py
+++ b/compiler/modules/bitcell_array.py
@@ -30,9 +30,18 @@ class bitcell_array(design.design):
         self.height = self.row_size*self.cell.height + drc["well_enclosure_active"]
         self.width = self.column_size*self.cell.width 
         
-        self.add_pins()
+        if(OPTS.bitcell == "pbitcell"):
+            self.add_multiport_pins()
+        else:
+            self.add_pins()
+        
         self.create_layout()
-        self.add_layout_pins()
+        
+        if(OPTS.bitcell == "pbitcell"):
+            self.add_multiport_layout_pins()
+        else:
+            self.add_layout_pins()
+        
         self.DRC_LVS()
 
     def add_pins(self):
@@ -43,6 +52,25 @@ class bitcell_array(design.design):
             self.add_pin("wl[{0}]".format(row))
         self.add_pin("vdd")
         self.add_pin("gnd")
+        
+    def add_multiport_pins(self):
+        self.num_write = self.cell.num_write
+        self.num_read = self.cell.num_read
+        
+        for col in range(self.column_size):
+            for k in range(self.num_write):
+                self.add_pin("wbl{0}[{1}]".format(k,col))
+                self.add_pin("wbl_bar{0}[{1}]".format(k,col))
+            for k in range(self.num_read):
+                self.add_pin("rbl{0}[{1}]".format(k,col))
+                self.add_pin("rbl_bar{0}[{1}]".format(k,col))
+        for row in range(self.row_size):
+            for k in range(self.num_write):
+                self.add_pin("wrow{0}[{1}]".format(k,row))
+            for k in range(self.num_read):
+                self.add_pin("rrow{0}[{1}]".format(k,row))
+        self.add_pin("vdd")
+        self.add_pin("gnd")
 
     def create_layout(self):
         xoffset = 0.0
@@ -58,16 +86,31 @@ class bitcell_array(design.design):
                 else:
                     tempy = yoffset
                     dir_key = ""
-
-                self.cell_inst[row,col]=self.add_inst(name=name,
-                                                      mod=self.cell,
-                                                      offset=[xoffset, tempy],
-                                                      mirror=dir_key)
-                self.connect_inst(["bl[{0}]".format(col),
-                                   "br[{0}]".format(col),
-                                   "wl[{0}]".format(row),
-                                   "vdd",
-                                   "gnd"])
+                
+                if(OPTS.bitcell == "pbitcell"):
+                    self.cell_inst[row,col]=self.add_inst(name=name,
+                                                          mod=self.cell,
+                                                          offset=[xoffset, tempy],
+                                                          mirror=dir_key)
+                    self.connect_inst(["wbl0[{0}]".format(col),
+                                       "wbl_bar0[{0}]".format(col),
+                                       "rbl0[{0}]".format(col),
+                                       "rbl_bar0[{0}]".format(col),
+                                       "wrow0[{0}]".format(row),
+                                       "rrow0[{0}]".format(row),
+                                       "vdd",
+                                       "gnd"])
+                else:
+                    self.cell_inst[row,col]=self.add_inst(name=name,
+                                                          mod=self.cell,
+                                                          offset=[xoffset, tempy],
+                                                          mirror=dir_key)
+                    self.connect_inst(["bl[{0}]".format(col),
+                                       "br[{0}]".format(col),
+                                       "wl[{0}]".format(row),
+                                       "vdd",
+                                       "gnd"])
+                                       
                 yoffset += self.cell.height
             xoffset += self.cell.width
 
@@ -161,6 +204,119 @@ class bitcell_array(design.design):
             # increments to the next row height
             offset.y += self.cell.height
 
+            
+    def add_multiport_layout_pins(self):
+        
+        # Our cells have multiple gnd pins for now.
+        # FIXME: fix for multiple vdd too
+        vdd_pin = self.cell.get_pin("vdd")
+
+        # shift it up by the overlap amount (gnd_pin) too
+        # must find the lower gnd pin to determine this overlap
+        lower_y = self.cell.height
+        gnd_pins = self.cell.get_pins("gnd")
+        for gnd_pin in gnd_pins:
+            if gnd_pin.layer=="metal2" and gnd_pin.by()<lower_y:
+                lower_y=gnd_pin.by()
+
+        # lower_y is negative, so subtract off double this amount for each pair of
+        # overlapping cells
+        full_height = self.height - 2*lower_y
+        
+        vdd_pin = self.cell.get_pin("vdd")
+        lower_x = vdd_pin.lx()
+        # lower_x is negative, so subtract off double this amount for each pair of
+        # overlapping cells
+        full_width = self.width - 2*lower_x
+        
+        offset = vector(0.0, 0.0)
+        for col in range(self.column_size):
+            # get the pin of the lower row cell and make it the full width
+            for k in range(self.num_write):
+                wbl_pin = self.cell_inst[0,col].get_pin("wbl{0}".format(k))
+                self.add_layout_pin(text="wbl{0}[{1}]".format(k,col),
+                                    layer="metal2",
+                                    offset=wbl_pin.ll(),
+                                    width=wbl_pin.width(),
+                                    height=full_height)
+                wbl_bar_pin = self.cell_inst[0,col].get_pin("wbl_bar{0}".format(k))
+                self.add_layout_pin(text="wbl_bar{0}[{1}]".format(k,col),
+                                    layer="metal2",
+                                    offset=wbl_bar_pin.ll(),
+                                    width=wbl_bar_pin.width(),
+                                    height=full_height)
+            for k in range(self.num_read):
+                rbl_pin = self.cell_inst[0,col].get_pin("rbl{0}".format(k))
+                self.add_layout_pin(text="rbl{0}[{1}]".format(k,col),
+                                    layer="metal2",
+                                    offset=rbl_pin.ll(),
+                                    width=rbl_pin.width(),
+                                    height=full_height)
+                rbl_bar_pin = self.cell_inst[0,col].get_pin("rbl_bar{0}".format(k))
+                self.add_layout_pin(text="rbl_bar{0}[{1}]".format(k,col),
+                                    layer="metal2",
+                                    offset=rbl_bar_pin.ll(),
+                                    width=rbl_bar_pin.width(),
+                                    height=full_height)
+
+            # gnd offset is 0 in our cell, but it be non-zero
+            gnd_pins = self.cell_inst[0,col].get_pins("gnd")
+            for gnd_pin in gnd_pins:
+                # avoid duplicates by only doing even rows
+                # also skip if it isn't the pin that spans the entire cell down to the bottom
+                if gnd_pin.layer=="metal2" and gnd_pin.by()==lower_y:
+                    self.add_layout_pin(text="gnd", 
+                                        layer="metal2",
+                                        offset=gnd_pin.ll(),
+                                        width=gnd_pin.width(),
+                                        height=full_height)
+                    
+            # increments to the next column width
+            offset.x += self.cell.width
+
+        offset.x = 0.0
+        for row in range(self.row_size):
+            vdd_pins = self.cell_inst[row,0].get_pins("vdd")
+            gnd_pins = self.cell_inst[row,0].get_pins("gnd")
+
+            for gnd_pin in gnd_pins:
+                if gnd_pin.layer=="metal1":
+                    self.add_layout_pin(text="gnd", 
+                                        layer="metal1",
+                                        offset=gnd_pin.ll(),
+                                        width=full_width,
+                                        height=drc["minwidth_metal1"])
+                
+            # add vdd label and offset
+            # only add to even rows to avoid duplicates
+            for vdd_pin in vdd_pins:
+                if row % 2 == 0 and vdd_pin.layer=="metal1":
+                    self.add_layout_pin(text="vdd",
+                                        layer="metal1",
+                                        offset=vdd_pin.ll(),
+                                        width=full_width,
+                                        height=drc["minwidth_metal1"])
+                
+            # add wl label and offset
+            for k in range(self.num_write):
+                wrow_pin = self.cell_inst[row,0].get_pin("wrow{0}".format(k))
+                self.add_layout_pin(text="wrow{0}[{1}]".format(k,row),
+                                    layer="metal1",
+                                    offset=wrow_pin.ll(),
+                                    width=full_width,
+                                    height=wrow_pin.height())
+                                    
+            for k in range(self.num_read):
+                rrow_pin = self.cell_inst[row,0].get_pin("rrow{0}".format(k))
+                self.add_layout_pin(text="rrow{0}[{1}]".format(k,row),
+                                    layer="metal1",
+                                    offset=rrow_pin.ll(),
+                                    width=full_width,
+                                    height=rrow_pin.height())
+
+            # increments to the next row height
+            offset.y += self.cell.height
+            
     def analytical_delay(self, slew, load=0):
         from tech import drc
         wl_wire = self.gen_wl_wire()