From 0e0516c4a620bfdf5d96a1935f599534d1df1f15 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 26 Jul 2018 16:45:09 -0700 Subject: [PATCH] Fix delay test unit test results. --- compiler/tests/21_ngspice_delay_test.py | 20 ++++++++++---------- compiler/tests/testutils.py | 2 +- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index fa20d893..d7d93562 100755 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -60,16 +60,16 @@ class timing_sram_test(openram_test): 'delay_hl': [0.3929995], 'slew_lh': [0.02160862]} elif OPTS.tech_name == "scn3me_subm": - golden_data = {'leakage_power': 0.00142014, - 'delay_lh': [0.8018421], - 'read0_power': [11.44908], - 'read1_power': [11.416549999999999], - 'write1_power': [11.718020000000001], - 'write0_power': [8.250219], - 'slew_hl': [0.8273725], - 'min_period': 34, - 'delay_hl': [1.085861], - 'slew_lh': [0.5730144]} + golden_data = {'delay_hl': [11.69536], + 'delay_lh': [1.260921], + 'leakage_power': 0.00039469710000000004, + 'min_period': 20.0, + 'read0_power': [4.40238], + 'read1_power': [4.126633], + 'slew_hl': [1.259555], + 'slew_lh': [0.9150649], + 'write0_power': [4.988347], + 'write1_power': [4.473887]} else: self.assertTrue(False) # other techs fail diff --git a/compiler/tests/testutils.py b/compiler/tests/testutils.py index 2d5de9f7..250483cf 100644 --- a/compiler/tests/testutils.py +++ b/compiler/tests/testutils.py @@ -79,7 +79,7 @@ class openram_test(unittest.TestCase): if not data_matches: import pprint data_string=pprint.pformat(data) - debug.info(0,"Consider replacing data in unit test with:\n"+data_string) + debug.info(0,"Data exceeded {:.1f}% tolerance:\n".format(error_tolerance*100)+data_string) return data_matches