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Fixed naming issues in trim_spice

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Bugra Onal
2023-02-03 16:36:14 -08:00
parent da86d50766
commit 0d60c76e3b
1 changed files with 4 additions and 3 deletions
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compiler/characterizer/trim_spice.py
+4 -3
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@@ -85,14 +85,15 @@ class trim_spice():
wl_regex = r"wl\d*_{}".format(wl_address)
bl_regex = r"bl\d*_{}".format(int(self.words_per_row*data_bit + col_address))
bl_no_port_regex = r"bl_{}".format(int(self.words_per_row*data_bit + col_address))
self.remove_insts("bitcell_array",[wl_regex,bl_regex])
# 2. Keep sense amps basd on BL
# FIXME: The bit lines are not indexed the same in sense_amp_array
#self.remove_insts("sense_amp_array",[bl_regex])
self.remove_insts("sense_amp_array",[bl_no_port_regex])
# 3. Keep column muxes basd on BL
self.remove_insts("column_mux_array", [bl_regex])
self.remove_insts("single_level_column_mux_array", [bl_no_port_regex])
# 4. Keep write driver based on DATA
data_regex = r"data_{}".format(data_bit)