From 0d60c76e3bfd1d37849004af2d33e9a0d7793fdc Mon Sep 17 00:00:00 2001 From: Bugra Onal Date: Fri, 3 Feb 2023 16:36:14 -0800 Subject: [PATCH] Fixed naming issues in trim_spice --- compiler/characterizer/trim_spice.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/compiler/characterizer/trim_spice.py b/compiler/characterizer/trim_spice.py index da2ce2ad..ca943318 100644 --- a/compiler/characterizer/trim_spice.py +++ b/compiler/characterizer/trim_spice.py @@ -85,14 +85,15 @@ class trim_spice(): wl_regex = r"wl\d*_{}".format(wl_address) bl_regex = r"bl\d*_{}".format(int(self.words_per_row*data_bit + col_address)) + bl_no_port_regex = r"bl_{}".format(int(self.words_per_row*data_bit + col_address)) + self.remove_insts("bitcell_array",[wl_regex,bl_regex]) # 2. Keep sense amps basd on BL - # FIXME: The bit lines are not indexed the same in sense_amp_array - #self.remove_insts("sense_amp_array",[bl_regex]) + self.remove_insts("sense_amp_array",[bl_no_port_regex]) # 3. Keep column muxes basd on BL - self.remove_insts("column_mux_array", [bl_regex]) + self.remove_insts("single_level_column_mux_array", [bl_no_port_regex]) # 4. Keep write driver based on DATA data_regex = r"data_{}".format(data_bit)