mirror of https://github.com/VLSIDA/OpenRAM.git
Set default port map
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parent
4e10f6d8a6
commit
0ccb3487b6
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@ -15,7 +15,7 @@ class cell:
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# Specifies if this is a hard (i.e. GDS) cell
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self._hard_cell = hard_cell
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self._boundary_layer = boundary_layer
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# Specifies the port directions
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self._port_types_map = {x: y for (x, y) in zip(port_order, port_types)}
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@ -23,7 +23,8 @@ class cell:
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# by default it is 1:1
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if not port_map:
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self._port_map = {x: x for x in port_order}
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else:
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self._port_map = port_map
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# Update mapping of names
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self._original_port_order = port_order
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self._port_order = port_order
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@ -81,8 +82,8 @@ class cell:
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def port_map(self, port_map):
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self._port_map = port_map
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# Update ordered name list to use the new names
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self._port_names = [self.port_map[x] for x in self._port_order]
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self._port_names = [self._port_map[x] for x in self._port_order]
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@property
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def body_bias(self):
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return self._body_bias
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@ -162,7 +162,7 @@ class options(optparse.Values):
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inv_dec = "pinv"
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nand2_dec = "pnand2"
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nand3_dec = "pnand3"
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nand4_dec = "pnand4" # Not available right now
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nand4_dec = "pnand4"
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precharge_array = "precharge_array"
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ptx = "ptx"
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replica_bitline = "replica_bitline"
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