From 0ccb3487b6577c9af512dffe9bd6887bd2892ab1 Mon Sep 17 00:00:00 2001
From: mrg <mrg@ucsc.edu>
Date: Tue, 24 Nov 2020 13:27:11 -0800
Subject: [PATCH] Set default port map

---
 compiler/base/custom_cell_properties.py | 9 +++++----
 compiler/options.py                     | 2 +-
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/compiler/base/custom_cell_properties.py b/compiler/base/custom_cell_properties.py
index 7b4d21c9..bb211842 100644
--- a/compiler/base/custom_cell_properties.py
+++ b/compiler/base/custom_cell_properties.py
@@ -15,7 +15,7 @@ class cell:
         # Specifies if this is a hard (i.e. GDS) cell
         self._hard_cell = hard_cell
         self._boundary_layer = boundary_layer
-        
+
         # Specifies the port directions
         self._port_types_map = {x: y for (x, y) in zip(port_order, port_types)}
         
@@ -23,7 +23,8 @@ class cell:
         # by default it is 1:1
         if not port_map:
             self._port_map = {x: x for x in port_order}
-
+        else:
+            self._port_map = port_map
         # Update mapping of names
         self._original_port_order = port_order
         self._port_order = port_order
@@ -81,8 +82,8 @@ class cell:
     def port_map(self, port_map):
         self._port_map = port_map
         # Update ordered name list to use the new names
-        self._port_names = [self.port_map[x] for x in self._port_order]
-    
+        self._port_names = [self._port_map[x] for x in self._port_order]
+        
     @property
     def body_bias(self):
         return self._body_bias
diff --git a/compiler/options.py b/compiler/options.py
index b5652e7e..e4a61052 100644
--- a/compiler/options.py
+++ b/compiler/options.py
@@ -162,7 +162,7 @@ class options(optparse.Values):
     inv_dec = "pinv"
     nand2_dec = "pnand2"
     nand3_dec = "pnand3"
-    nand4_dec = "pnand4" # Not available right now
+    nand4_dec = "pnand4"
     precharge_array = "precharge_array"
     ptx = "ptx"
     replica_bitline = "replica_bitline"