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Set default port map

This commit is contained in:
mrg 2020-11-24 13:27:11 -08:00
parent 4e10f6d8a6
commit 0ccb3487b6
2 changed files with 6 additions and 5 deletions
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5
compiler/base/custom_cell_properties.py
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@ -23,7 +23,8 @@ class cell:
# by default it is 1:1 # by default it is 1:1
if not port_map: if not port_map:
self._port_map = {x: x for x in port_order} self._port_map = {x: x for x in port_order}
else:
self._port_map = port_map
# Update mapping of names # Update mapping of names
self._original_port_order = port_order self._original_port_order = port_order
self._port_order = port_order self._port_order = port_order
@ -81,7 +82,7 @@ class cell:
def port_map(self, port_map): def port_map(self, port_map):
self._port_map = port_map self._port_map = port_map
# Update ordered name list to use the new names # Update ordered name list to use the new names
self._port_names = [self.port_map[x] for x in self._port_order] self._port_names = [self._port_map[x] for x in self._port_order]
@property @property
def body_bias(self): def body_bias(self):

2
compiler/options.py
View File

@ -162,7 +162,7 @@ class options(optparse.Values):
inv_dec = "pinv" inv_dec = "pinv"
nand2_dec = "pnand2" nand2_dec = "pnand2"
nand3_dec = "pnand3" nand3_dec = "pnand3"
nand4_dec = "pnand4" # Not available right now nand4_dec = "pnand4"
precharge_array = "precharge_array" precharge_array = "precharge_array"
ptx = "ptx" ptx = "ptx"
replica_bitline = "replica_bitline" replica_bitline = "replica_bitline"