From 0cb86b8ba29a3b7b4889ceef8d2b3588891939eb Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 3 Jul 2019 14:46:20 -0700 Subject: [PATCH] Exclude new precharge in graph build --- compiler/modules/bank.py | 6 +++--- compiler/modules/port_data.py | 5 ++++- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 9b78f2dd..9a274cd1 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -1014,9 +1014,9 @@ class bank(design.design): def graph_exclude_precharge(self): """Precharge adds a loop between bitlines, can be excluded to reduce complexity""" - for inst in self.precharge_array_inst: - if inst != None: - self.graph_inst_exclude.add(inst) + for port in self.read_ports: + if self.port_data[port]: + self.port_data[port].graph_exclude_precharge() def get_cell_name(self, inst_name, row, col): """Gets the spice name of the target bitcell.""" diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 3737892c..a03741c4 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -494,4 +494,7 @@ class port_data(design.design): self.add_path("metal2",[bottom_br, vector(bottom_br.x,yoffset), vector(top_br.x,yoffset), top_br]) - + def graph_exclude_precharge(self): + """Precharge adds a loop between bitlines, can be excluded to reduce complexity""" + if self.precharge_array_inst: + self.graph_inst_exclude.add(self.precharge_array_inst)