From 0c3c58011bfeb6759da679534766be50bc8286e8 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Wed, 5 Dec 2018 00:13:23 -0800 Subject: [PATCH] Fixed delay test values. --- compiler/characterizer/delay.py | 3 +- compiler/characterizer/stimuli.py | 5 ++-- compiler/tests/21_hspice_delay_test.py | 40 ++++++++++++------------- compiler/tests/21_ngspice_delay_test.py | 40 ++++++++++++------------- 4 files changed, 45 insertions(+), 43 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 3f000374..9e0543d1 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -569,6 +569,7 @@ class delay(simulation): #Update target target_period = 0.5 * (ub_period + lb_period) + #key=input("press return to continue") def try_period(self, feasible_delays): @@ -590,7 +591,7 @@ class delay(simulation): #Delays/slews based on the period will cause the min_period search to come to the wrong period. if self.sram.col_addr_size>0 and "slew" in dname: continue - + if not relative_compare(results[port][dname],feasible_delays[port][dname],error_tolerance=0.05): debug.info(2,"Delay too big {0} vs {1}".format(results[port][dname],feasible_delays[port][dname])) return False diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index 6fa7a481..e5b24387 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -244,9 +244,10 @@ class stimuli(): reltol = 0.005 # 0.5% else: reltol = 0.001 # 0.1% - + timestep = 10 #ps, was 5ps but ngspice was complaining the timestep was too small in certain tests. + # UIC is needed for ngspice to converge - self.sf.write(".TRAN 5p {0}n UIC\n".format(end_time)) + self.sf.write(".TRAN {0}p {1}n UIC\n".format(timestep,end_time)) if OPTS.spice_name == "ngspice": # ngspice sometimes has convergence problems if not using gear method # which is more accurate, but slower than the default trapezoid method diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index 2a212538..32680e2f 100755 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -50,27 +50,27 @@ class timing_sram_test(openram_test): data.update(port_data[0]) if OPTS.tech_name == "freepdk45": - golden_data = {'delay_hl': [0.15801], - 'delay_lh': [0.15801], - 'leakage_power': 0.0023949, - 'min_period': 0.41, - 'read0_power': [0.628], - 'read1_power': [0.60328], - 'slew_hl': [0.092516], - 'slew_lh': [0.092516], - 'write0_power': [0.7510600000000001], - 'write1_power': [0.66619]} + golden_data = {'delay_hl': [0.2011], + 'delay_lh': [0.2011], + 'leakage_power': 0.0014218000000000002, + 'min_period': 0.41, + 'read0_power': [0.63604], + 'read1_power': [0.6120599999999999], + 'slew_hl': [0.10853], + 'slew_lh': [0.10853], + 'write0_power': [0.51742], + 'write1_power': [0.51095]} elif OPTS.tech_name == "scn4m_subm": - golden_data = {'delay_hl': [1.2], - 'delay_lh': [1.2], - 'leakage_power': 0.026912, - 'min_period': 2.891, - 'read0_power': [24.7996], - 'read1_power': [23.9464], - 'slew_hl': [0.7045815], - 'slew_lh': [0.7045815], - 'write0_power': [27.8985], - 'write1_power': [25.1812]} + golden_data = {'delay_hl': [1.3911], + 'delay_lh': [1.3911], + 'leakage_power': 0.0278488, + 'min_period': 2.812, + 'read0_power': [22.1183], + 'read1_power': [21.4388], + 'slew_hl': [0.7397553], + 'slew_lh': [0.7397553], + 'write0_power': [19.4103], + 'write1_power': [20.1167]} else: self.assertTrue(False) # other techs fail # Check if no too many or too few results diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index 96b1c887..26e5b2c0 100755 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -50,27 +50,27 @@ class timing_sram_test(openram_test): data.update(port_data[0]) if OPTS.tech_name == "freepdk45": - golden_data = {'delay_hl': [0.1587689], - 'delay_lh': [0.1587689], - 'leakage_power': 0.02824871, - 'min_period': 0.43, - 'read0_power': [0.5932789], - 'read1_power': [0.5733669], - 'slew_hl': [0.09096027999999999], - 'slew_lh': [0.09096027999999999], - 'write0_power': [0.7133274], - 'write1_power': [0.6390777]} + golden_data = {'delay_hl': [0.20443139999999999], + 'delay_lh': [0.20443139999999999], + 'leakage_power': 0.0017840640000000001, + 'min_period': 0.41, + 'read0_power': [0.6435831], + 'read1_power': [0.6233463], + 'slew_hl': [0.1138734], + 'slew_lh': [0.1138734], + 'write0_power': [0.5205761], + 'write1_power': [0.5213689]} elif OPTS.tech_name == "scn4m_subm": - golden_data = {'delay_hl': [1.342843], - 'delay_lh': [1.342843], - 'leakage_power': 0.001683033, - 'min_period': 3.906, - 'read0_power': [19.55096], - 'read1_power': [18.99015], - 'slew_hl': [0.7687596], - 'slew_lh': [0.7687596], - 'write0_power': [22.285880000000002], - 'write1_power': [19.97167]} + golden_data = {'delay_hl': [1.610911], + 'delay_lh': [1.610911], + 'leakage_power': 0.0023593859999999998, + 'min_period': 3.281, + 'read0_power': [20.763569999999998], + 'read1_power': [20.32745], + 'slew_hl': [0.7986348999999999], + 'slew_lh': [0.7986348999999999], + 'write0_power': [17.58272], + 'write1_power': [18.523419999999998]} else: self.assertTrue(False) # other techs fail