fix merge conflicts

compiler/pgates/pand2.py

@@ -30,13 +30,12 @@ class pand2(pgate.pgate):
         self.create_insts()
 
     def create_modules(self):
-        # Shield the cap, but have at least a stage effort of 4
         self.nand = factory.create(module_type="pnand2", height=self.height)
         self.add_mod(self.nand)
 
         self.inv = factory.create(module_type="pdriver",
                                   neg_polarity=True,
-                                  fanout=3*self.size,
+                                  fanout=self.size,
                                   height=self.height)
         self.add_mod(self.inv)
 
@@ -45,6 +44,7 @@ class pand2(pgate.pgate):
         self.place_insts()
         self.add_wires()
         self.add_layout_pins()
+        self.add_boundary()
         self.DRC_LVS()
         
     def add_pins(self):

compiler/pgates/pand3.py

@@ -44,6 +44,7 @@ class pand3(pgate.pgate):
         self.place_insts()
         self.add_wires()
         self.add_layout_pins()
+        self.add_boundary()
         self.DRC_LVS()
         
     def add_pins(self):

compiler/pgates/pbuf.py

@@ -37,6 +37,7 @@ class pbuf(pgate.pgate):
         self.place_insts()
         self.add_wires()
         self.add_layout_pins()
+        self.add_boundary()
         
     def add_pins(self):
         self.add_pin("A", "INPUT")

compiler/pgates/pdriver.py

@@ -76,6 +76,7 @@ class pdriver(pgate.pgate):
 
         self.width = self.inv_inst_list[-1].rx()
         self.height = self.inv_inst_list[0].height
+        self.add_boundary()
         
     def add_pins(self):
         self.add_pin("A", "INPUT")

compiler/pgates/pinv.py

@@ -68,6 +68,7 @@ class pinv(pgate.pgate):
                               "A",
                               position="farleft")
         self.route_outputs()
+        self.add_boundary()
         
     def add_pins(self):
         """ Adds pins for spice netlist """

compiler/pgates/pinvbuf.py

@@ -47,6 +47,7 @@ class pinvbuf(pgate.pgate):
         self.place_modules()
         self.route_wires()
         self.add_layout_pins()
+        self.add_boundary()
         
         self.offset_all_coordinates()
         

compiler/pgates/pnand2.py

@@ -62,7 +62,8 @@ class pnand2(pgate.pgate):
         self.extend_wells()
         self.route_inputs()
         self.route_output()
-
+        self.add_boundary()
+        
     def add_pins(self):
         """ Adds pins for spice netlist """
         pin_list = ["A", "B", "Z", "vdd", "gnd"]

compiler/pgates/pnand3.py

@@ -70,6 +70,7 @@ class pnand3(pgate.pgate):
         self.extend_wells()
         self.route_inputs()
         self.route_output()
+        self.add_boundary()
         
     def add_ptx(self):
         """ Create the PMOS and NMOS transistors. """

compiler/pgates/pnor2.py

@@ -61,6 +61,7 @@ class pnor2(pgate.pgate):
         self.extend_wells()
         self.route_inputs()
         self.route_output()
+        self.add_boundary()
 
     def add_pins(self):
         """ Adds pins for spice netlist """

compiler/pgates/precharge.py

@@ -70,7 +70,8 @@ class precharge(design.design):
         self.route_vdd_rail()
         self.route_bitlines()
         self.connect_to_bitlines()
-
+        self.add_boundary()
+        
     def add_pins(self):
         self.add_pin_list(["bl", "br", "en_bar", "vdd"],
                           ["OUTPUT", "OUTPUT", "INPUT", "POWER"])

compiler/pgates/ptristate_inv.py

@@ -56,6 +56,7 @@ class ptristate_inv(pgate.pgate):
         self.connect_rails()
         self.route_inputs()
         self.route_outputs()
+        self.add_boundary()
         
     def add_pins(self):
         """ Adds pins for spice netlist """

compiler/pgates/pwrite_driver.py

@@ -52,6 +52,7 @@ class pwrite_driver(design.design):
         self.place_modules()
         self.route_wires()
         self.route_supplies()
+        self.add_boundary()
         
     def add_pins(self):
         self.add_pin("din", "INPUT")