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https://github.com/VLSIDA/OpenRAM.git
synced 2026-08-29 09:30:38 +02:00
Fix errors in new run_sim calls and corners
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@@ -46,8 +46,7 @@ class sram_1bank_4mux_func_test(openram_test):
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tempspice = OPTS.openram_temp + "sram.sp"
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s.sp_write(tempspice)
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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f = functional(s.s, tempspice, corner)
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f = functional(s.s, tempspice)
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(fail, error) = f.run()
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self.assertTrue(fail, error)
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@@ -49,8 +49,7 @@ class sram_1bank_8mux_func_test(openram_test):
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tempspice = OPTS.openram_temp + "sram.sp"
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s.sp_write(tempspice)
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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f = functional(s.s, tempspice, corner)
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f = functional(s.s, tempspice)
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(fail, error) = f.run()
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self.assertTrue(fail, error)
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@@ -49,8 +49,7 @@ class psram_1bank_nomux_func_test(openram_test):
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tempspice = OPTS.openram_temp + "sram.sp"
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s.sp_write(tempspice)
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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f = functional(s.s, tempspice, corner)
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f = functional(s.s, tempspice)
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(fail, error) = f.run()
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self.assertTrue(fail, error)
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@@ -45,8 +45,7 @@ class sram_1bank_nomux_func_test(openram_test):
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tempspice = OPTS.openram_temp + "sram.sp"
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s.sp_write(tempspice)
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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f = functional(s.s, tempspice, corner)
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f = functional(s.s, tempspice)
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(fail, error) = f.run()
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self.assertTrue(fail, error)
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@@ -46,8 +46,7 @@ class sram_1bank_nomux_sparecols_func_test(openram_test):
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tempspice = OPTS.openram_temp + "sram.sp"
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s.sp_write(tempspice)
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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f = functional(s.s, tempspice, corner)
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f = functional(s.s, tempspice)
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(fail, error) = f.run()
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self.assertTrue(fail, error)
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@@ -52,8 +52,7 @@ class sram_wmask_1w_1r_func_test(openram_test):
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tempspice = OPTS.openram_temp + "sram.sp"
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s.sp_write(tempspice)
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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f = functional(s.s, tempspice, corner)
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f = functional(s.s, tempspice)
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(fail, error) = f.run()
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self.assertTrue(fail, error)
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@@ -48,8 +48,7 @@ class sram_wmask_func_test(openram_test):
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tempspice = OPTS.openram_temp + "sram.sp"
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s.sp_write(tempspice)
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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f = functional(s.s, tempspice, corner)
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f = functional(s.s, tempspice)
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(fail, error) = f.run()
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self.assertTrue(fail, error)
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@@ -77,7 +77,7 @@ class hspice_pex_pinv_test(openram_test):
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sim_file = OPTS.openram_temp + "stim.sp"
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log_file_name = "timing"
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test_sim = self.write_simulation(sim_file, test_module, top_level_name)
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test_sim.run_sim()
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test_sim.run_sim("stim.sp")
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delay = parse_spice_list(log_file_name, "pinv_delay")
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return delay
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@@ -76,7 +76,7 @@ class ngspice_pex_pinv_test(openram_test):
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sim_file = OPTS.openram_temp + "stim.sp"
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log_file_name = "timing"
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test_sim = self.write_simulation(sim_file, test_module, top_level_name)
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test_sim.run_sim()
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test_sim.run_sim("stim.sp")
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delay = parse_spice_list(log_file_name, "pinv_delay")
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return delay
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