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Change num_wmask to num_wmasks and write_size = None not word_size if wmask not used.

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jsowash
2019-07-19 14:58:37 -07:00
parent 45cb159d7f
commit 0a5461201a
13 changed files with 91 additions and 138 deletions
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compiler/sram/sram_1bank.py
+4 -4
View File
@@ -46,7 +46,7 @@ class sram_1bank(sram_base):
self.data_dff_insts = self.create_data_dff()
if (self.write_size != self.word_size):
if self.write_size is not None:
self.wmask_dff_insts = self.create_wmask_dff()
@@ -126,7 +126,7 @@ class sram_1bank(sram_base):
self.data_dff_insts[port].place(data_pos[port])
# Add the write mask flops to the left of the din flops.
if (self.write_size != self.word_size):
if self.write_size is not None:
if port in self.write_ports:
wmask_pos[port] = vector(self.bank.bank_array_ll.x - self.control_logic_insts[port].width,
-max_gap_size - self.wmask_dff_insts[port].height)
@@ -148,7 +148,7 @@ class sram_1bank(sram_base):
self.data_dff_insts[port].place(data_pos[port], mirror="MX")
# Add the write mask flops to the left of the din flops.
if (self.write_size != self.word_size):
if self.write_size is not None:
if port in self.write_ports:
wmask_pos[port] = vector(self.bank.bank_array_ur.x - self.data_dff_insts[port].width,
self.bank.height + max_gap_size + self.data_dff_insts[port].height)
@@ -362,7 +362,7 @@ class sram_1bank(sram_base):
#Data dffs and wmask dffs are only for writing so are not useful for evaluating read delay.
for inst in self.data_dff_insts:
self.graph_inst_exclude.add(inst)
if (self.write_size != self.word_size):
if self.write_size is not None:
for inst in self.wmask_dff_insts:
self.graph_inst_exclude.add(inst)
compiler/sram/sram_base.py
+17 -21
View File
@@ -34,13 +34,18 @@ class sram_base(design, verilog, lef):
sram_config.set_local_config(self)
self.bank_insts = []
if self.write_size is not None:
self.num_wmasks = int(self.word_size/self.write_size)
else:
self.num_wmasks = 0
#For logical effort delay calculations.
self.all_mods_except_control_done = False
def add_pins(self):
""" Add pins for entire SRAM. """
self.num_masks = int(self.word_size/self.write_size)
for port in self.write_ports:
for bit in range(self.word_size):
self.add_pin("DIN{0}[{1}]".format(port,bit),"INPUT")
@@ -70,10 +75,9 @@ class sram_base(design, verilog, lef):
for port in self.all_ports:
self.add_pin("clk{}".format(port),"INPUT")
# add the optional write mask pins
if self.word_size != self.write_size:
for port in self.write_ports:
for bit in range(self.num_masks):
self.add_pin("wmask{0}[{1}]".format(port,bit),"INPUT")
for port in self.write_ports:
for bit in range(self.num_wmasks):
self.add_pin("wmask{0}[{1}]".format(port,bit),"INPUT")
for port in self.read_ports:
for bit in range(self.word_size):
self.add_pin("DOUT{0}[{1}]".format(port,bit),"OUTPUT")
@@ -280,9 +284,8 @@ class sram_base(design, verilog, lef):
self.data_dff = dff_array(name="data_dff", rows=1, columns=self.word_size)
self.add_mod(self.data_dff)
if (self.write_size != self.word_size):
num_wmask = int(self.word_size/self.write_size)
self.wmask_dff = dff_array(name="wmask_dff", rows=1, columns=num_wmask)
if self.write_size is not None:
self.wmask_dff = dff_array(name="wmask_dff", rows=1, columns=self.num_wmasks)
self.add_mod(self.wmask_dff)
@@ -312,23 +315,20 @@ class sram_base(design, verilog, lef):
self.control_logic_rw = self.mod_control_logic(num_rows=self.num_rows,
words_per_row=self.words_per_row,
word_size=self.word_size,
write_size = self.write_size,
sram=self,
sram=self,
port_type="rw")
self.add_mod(self.control_logic_rw)
if len(self.writeonly_ports)>0:
self.control_logic_w = self.mod_control_logic(num_rows=self.num_rows,
words_per_row=self.words_per_row,
word_size=self.word_size,
write_size=self.write_size,
sram=self,
sram=self,
port_type="w")
self.add_mod(self.control_logic_w)
if len(self.readonly_ports)>0:
self.control_logic_r = self.mod_control_logic(num_rows=self.num_rows,
words_per_row=self.words_per_row,
word_size=self.word_size,
write_size=self.write_size,
sram=self,
port_type="r")
self.add_mod(self.control_logic_r)
@@ -357,11 +357,8 @@ class sram_base(design, verilog, lef):
temp.append("p_en_bar{0}".format(port))
for port in self.write_ports:
temp.append("w_en{0}".format(port))
if (self.word_size != self.write_size):
for bit in range(self.num_masks):
temp.append("bank_wmask{}[{}]".format(port, bit))
# for bit in range(self.num_masks):
# temp.append("wdriver_sel{}[{}]".format(port, bit))
for bit in range(self.num_wmasks):
temp.append("bank_wmask{}[{}]".format(port, bit))
for port in self.all_ports:
temp.append("wl_en{0}".format(port))
temp.extend(["vdd", "gnd"])
@@ -463,7 +460,6 @@ class sram_base(design, verilog, lef):
def create_wmask_dff(self):
""" Add and place all wmask flops """
num_wmask = int(self.word_size/self.write_size)
insts = []
for port in self.all_ports:
if port in self.write_ports:
@@ -476,7 +472,7 @@ class sram_base(design, verilog, lef):
# inputs, outputs/output/bar
inputs = []
outputs = []
for bit in range(num_wmask):
for bit in range(self.num_wmasks):
inputs.append("wmask{}[{}]".format(port, bit))
outputs.append("bank_wmask{}[{}]".format(port, bit))
compiler/sram/sram_config.py
+1 -26
View File
@@ -23,8 +23,6 @@ class sram_config:
# This will get over-written when we determine the organization
self.words_per_row = words_per_row
if self.write_size == None:
self.write_size = self.word_size
self.compute_sizes()
@@ -64,26 +62,7 @@ class sram_config:
self.words_per_row = self.amend_words_per_row(self.tentative_num_rows, self.words_per_row)
debug.info(1,"Words per row: {}".format(self.words_per_row))
self.recompute_sizes_once()
def recompute_sizes_once(self):
"""
Calculate the auxiliary values assuming fixed number of words per row.
"""
# If the banks changed
self.num_words_per_bank = self.num_words / self.num_banks
self.num_bits_per_bank = self.word_size * self.num_words_per_bank
# Fix the number of columns and rows
self.num_cols = int(self.words_per_row * self.word_size)
self.num_rows = int(self.num_words_per_bank / self.words_per_row)
# Compute the address and bank sizes
self.row_addr_size = int(log(self.num_rows, 2))
self.col_addr_size = int(log(self.words_per_row, 2))
self.bank_addr_size = self.col_addr_size + self.row_addr_size
self.addr_size = self.bank_addr_size + int(log(self.num_banks, 2))
self.recompute_sizes()
def recompute_sizes(self):
"""
@@ -92,10 +71,6 @@ class sram_config:
SRAM for testing.
"""
# This function is ran without the write mask option, but word_size can be redefined
# which makes the tests think there is a write mask.
self.write_size = self.word_size
# If the banks changed
self.num_words_per_bank = self.num_words/self.num_banks
self.num_bits_per_bank = self.word_size*self.num_words_per_bank