From 0a5461201a530e04fd6cd504700ff74324903ece Mon Sep 17 00:00:00 2001 From: jsowash Date: Fri, 19 Jul 2019 14:58:37 -0700 Subject: [PATCH] Change num_wmask to num_wmasks and write_size = None not word_size if wmask not used. --- compiler/base/verilog.py | 40 ++++++++++------------- compiler/characterizer/functional.py | 25 +++++++------- compiler/characterizer/simulation.py | 18 +++++----- compiler/modules/bank.py | 23 +++++-------- compiler/modules/control_logic.py | 9 +---- compiler/modules/multibank.py | 2 +- compiler/modules/port_data.py | 23 +++++++------ compiler/modules/write_driver_array.py | 6 ++-- compiler/modules/write_mask_and_array.py | 8 ++--- compiler/sram/sram_1bank.py | 8 ++--- compiler/sram/sram_base.py | 38 ++++++++++----------- compiler/sram/sram_config.py | 27 +-------------- compiler/tests/22_sram_wmask_func_test.py | 2 +- 13 files changed, 91 insertions(+), 138 deletions(-) diff --git a/compiler/base/verilog.py b/compiler/base/verilog.py index c4d4ee00..a11ffd0a 100644 --- a/compiler/base/verilog.py +++ b/compiler/base/verilog.py @@ -18,15 +18,11 @@ class verilog: def verilog_write(self,verilog_name): """ Write a behavioral Verilog model. """ self.vf = open(verilog_name, "w") - # Determine if optional write mask is used - self.wmask_enabled = False - if self.word_size != self.write_size: - self.wmask_enabled = True self.vf.write("// OpenRAM SRAM model\n") self.vf.write("// Words: {0}\n".format(self.num_words)) self.vf.write("// Word size: {0}\n".format(self.word_size)) - if self.wmask_enabled: + if self.write_size is not None: self.vf.write("// Write size: {0}\n\n".format(self.write_size)) else: self.vf.write("\n") @@ -41,12 +37,12 @@ class verilog: self.vf.write("// Port {0}: W\n".format(port)) if port in self.readwrite_ports: self.vf.write(" clk{0},csb{0},web{0},".format(port)) - if self.wmask_enabled: + if self.write_size is not None: self.vf.write("wmask{},".format(port)) self.vf.write("ADDR{0},DIN{0},DOUT{0}".format(port)) elif port in self.write_ports: self.vf.write(" clk{0},csb{0},".format(port)) - if self.wmask_enabled: + if self.write_size is not None: self.vf.write("wmask{},".format(port)) self.vf.write("ADDR{0},DIN{0}".format(port)) elif port in self.read_ports: @@ -56,11 +52,11 @@ class verilog: self.vf.write(",\n") self.vf.write("\n );\n\n") - if self.wmask_enabled: - self.num_wmask = int(self.word_size/self.write_size) - self.vf.write(" parameter NUM_WMASK = {0} ;\n".format(self.num_wmask)) + if self.write_size is not None: + self.num_wmasks = int(self.word_size/self.write_size) + self.vf.write(" parameter NUM_WMASKS = {0} ;\n".format(self.num_wmasks)) self.vf.write(" parameter DATA_WIDTH = {0} ;\n".format(self.word_size)) - self.vf.write(" parameter ADDR_WIDTH = {0} ;\n".format(self.addr_size)) + self.vf.write(" parameter ADDR_WIDTH = {0} ;\n".format(self.addr_sizeaddr_size)) self.vf.write(" parameter RAM_DEPTH = 1 << ADDR_WIDTH;\n") self.vf.write(" // FIXME: This delay is arbitrary.\n") self.vf.write(" parameter DELAY = 3 ;\n") @@ -103,8 +99,8 @@ class verilog: if port in self.readwrite_ports: self.vf.write(" reg web{0}_reg;\n".format(port)) if port in self.write_ports: - if self.wmask_enabled: - self.vf.write(" reg [NUM_WMASK-1:0] wmask{0}_reg;\n".format(port)) + if self.write_size is not None: + self.vf.write(" reg [NUM_WMASKS-1:0] wmask{0}_reg;\n".format(port)) self.vf.write(" reg [ADDR_WIDTH-1:0] ADDR{0}_reg;\n".format(port)) if port in self.write_ports: self.vf.write(" reg [DATA_WIDTH-1:0] DIN{0}_reg;\n".format(port)) @@ -123,7 +119,7 @@ class verilog: if port in self.readwrite_ports: self.vf.write(" web{0}_reg = web{0};\n".format(port)) if port in self.write_ports: - if self.wmask_enabled: + if self.write_size is not None: self.vf.write(" wmask{0}_reg = wmask{0};\n".format(port)) self.vf.write(" ADDR{0}_reg = ADDR{0};\n".format(port)) if port in self.write_ports: @@ -138,13 +134,13 @@ class verilog: self.vf.write(" $display($time,\" Reading %m ADDR{0}=%b DOUT{0}=%b\",ADDR{0}_reg,mem[ADDR{0}_reg]);\n".format(port)) if port in self.readwrite_ports: self.vf.write(" if ( !csb{0}_reg && !web{0}_reg )\n".format(port)) - if self.wmask_enabled: + if self.write_size is not None: self.vf.write(" $display($time,\" Writing %m ADDR{0}=%b DIN{0}=%b wmask{0}=%b\",ADDR{0}_reg,DIN{0}_reg,wmask{0}_reg);\n".format(port)) else: self.vf.write(" $display($time,\" Writing %m ADDR{0}=%b DIN{0}=%b\",ADDR{0}_reg,DIN{0}_reg);\n".format(port)) elif port in self.write_ports: self.vf.write(" if ( !csb{0}_reg )\n".format(port)) - if self.wmask_enabled: + if self.write_size is not None: self.vf.write(" $display($time,\" Writing %m ADDR{0}=%b DIN{0}=%b wmask{0}=%b\",ADDR{0}_reg,DIN{0}_reg,wmask{0}_reg);\n".format(port)) else: self.vf.write(" $display($time,\" Writing %m ADDR{0}=%b DIN{0}=%b\",ADDR{0}_reg,DIN{0}_reg);\n".format(port)) @@ -160,8 +156,8 @@ class verilog: self.vf.write(" input csb{0}; // active low chip select\n".format(port)) if port in self.readwrite_ports: self.vf.write(" input web{0}; // active low write control\n".format(port)) - if (self.wmask_enabled): - self.vf.write(" input [NUM_WMASK-1:0] wmask{0}; // write mask\n".format(port)) + if self.write_size is not None: + self.vf.write(" input [NUM_WMASKS-1:0] wmask{0}; // write mask\n".format(port)) self.vf.write(" input [ADDR_WIDTH-1:0] ADDR{0};\n".format(port)) if port in self.write_ports: self.vf.write(" input [DATA_WIDTH-1:0] DIN{0};\n".format(port)) @@ -179,18 +175,18 @@ class verilog: self.vf.write(" always @ (negedge clk{0})\n".format(port)) self.vf.write(" begin : MEM_WRITE{0}\n".format(port)) if port in self.readwrite_ports: - if self.wmask_enabled: + if self.write_size is not None: self.vf.write(" if ( !csb{0}_reg && !web{0}_reg ) begin\n".format(port)) else: self.vf.write(" if ( !csb{0}_reg && !web{0}_reg )\n".format(port)) else: - if self.wmask_enabled: + if self.write_size is not None: self.vf.write(" if (!csb{0}_reg) begin\n".format(port)) else: self.vf.write(" if (!csb{0}_reg)\n".format(port)) - if self.wmask_enabled: - for mask in range(0,self.num_wmask): + if self.write_size is not None: + for mask in range(0,self.num_wmasks): lower = mask * self.write_size upper = lower + self.write_size-1 self.vf.write(" if (wmask{0}_reg[{1}])\n".format(port,mask)) diff --git a/compiler/characterizer/functional.py b/compiler/characterizer/functional.py index 87ba0678..8389fdea 100644 --- a/compiler/characterizer/functional.py +++ b/compiler/characterizer/functional.py @@ -32,6 +32,11 @@ class functional(simulation): if OPTS.is_unit_test: random.seed(12345) + if self.write_size is not None: + self.num_wmasks = int(self.word_size / self.write_size) + else: + self.num_wmasks = 0 + self.set_corner(corner) self.set_spice_constants() #self.set_feasible_period(sram, spfile, corner) @@ -46,13 +51,10 @@ class functional(simulation): self.read_check = [] def initilize_wmask(self): - self.wmask = [None]*self.num_wmask - self.num_wmask = int(self.word_size/self.write_size) - self.wmask_enabled = False - if self.word_size !=self.write_size: - self.wmask_enabled = True + self.wmask = [None]*self.num_wmasks + if self.write_size is not None: # initialize wmask to 1 - for bit in range(self.num_wmask): + for bit in range(self.num_wmasks): self.wmask[bit] = 1 # if bit == 0: # self.wmask[self.num_wmask-1 - bit] = 1 @@ -189,8 +191,8 @@ class functional(simulation): return(1, "SUCCESS") def gen_wmask(self): - wmask_bits = [None]*self.num_wmask - for bit in range(self.num_wmask): + wmask_bits = [None]*self.num_wmasks + for bit in range(self.num_wmasks): rand = random.randint(0, 1) wmask_bits[bit] = rand return wmask_bits @@ -292,10 +294,9 @@ class functional(simulation): # Generate wmask bits for port in self.write_ports: - self.sf.write("\n* Generation of wmask signals\n") - if (self.write_size != self.word_size): - num_wmask = int(self.word_size / self.write_size) - for bit in range(num_wmask): + self.sf.write("\n* Generation of wmask sibfssgnals\n") + if self.write_size is not None: + for bit in range(self.num_wmasks): sig_name = "WMASK{0}_{1} ".format(port, bit) self.stim.gen_pwl(sig_name, self.cycle_times, self.data_values[port][bit], self.period, self.slew, 0.05) diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py index 4dee96df..c75783b3 100644 --- a/compiler/characterizer/simulation.py +++ b/compiler/characterizer/simulation.py @@ -34,10 +34,11 @@ class simulation(): self.readwrite_ports = self.sram.readwrite_ports self.read_ports = self.sram.read_ports self.write_ports = self.sram.write_ports - self.num_wmask = int(self.word_size/self.write_size) - self.wmask_enabled = False - if self.word_size !=self.write_size: - self.wmask_enabled = True + if self.write_size is not None: + self.num_wmasks = int(self.word_size/self.write_size) + else: + self.num_wmasks = 0 + def set_corner(self,corner): """ Set the corner values """ @@ -79,7 +80,7 @@ class simulation(): # Three dimensional list to handle each addr and data bits for wach port over the number of checks self.addr_values = [[[] for bit in range(self.addr_size)] for port in self.all_ports] self.data_values = [[[] for bit in range(self.word_size)] for port in self.write_ports] - self.wmask_values = [[[] for bit in range(self.num_wmask)] for port in self.write_ports] + self.wmask_values = [[[] for bit in range(self.num_wmasks)] for port in self.write_ports] # For generating comments in SPICE stimulus self.cycle_comments = [] @@ -248,7 +249,7 @@ class simulation(): t_current, t_current+self.period) elif op == "write": - if (self.wmask_enabled): + if self.write_size is not None: comment = "\tWriting {0} to address {1} with mask bit {2} (from port {3}) during cycle {4} ({5}ns - {6}ns)".format(word, addr, wmask, @@ -300,9 +301,8 @@ class simulation(): for port in range(total_ports): pin_names.append("{0}{1}".format(tech.spice["clk"], port)) - if (self.write_size != self.word_size): - num_wmask = int(self.word_size/self.write_size) - for bit in range(num_wmask): + if self.write_size is not None: + for bit in range(self.num_wmasks): pin_names.append("WMASK{0}_{1}".format(port,bit)) for read_output in read_index: diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index f62c9f8a..f4f1cabe 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -30,8 +30,10 @@ class bank(design.design): self.sram_config = sram_config sram_config.set_local_config(self) - if (self.word_size != self.write_size): - self.num_wmask = int(self.word_size/self.write_size) + if self.write_size is not None: + self.num_wmasks = int(self.word_size/self.write_size) + else: + self.num_wmasks = 0 if name == "": name = "bank_{0}_{1}".format(self.word_size, self.num_words) @@ -82,9 +84,6 @@ class bank(design.design): for port in self.write_ports: for bit in range(self.word_size): self.add_pin("din{0}_{1}".format(port,bit),"IN") - # if (self.word_size != self.write_size): - # for bit in range(self.word_size): - # self.add_pin() for port in self.all_ports: for bit in range(self.addr_size): self.add_pin("addr{0}_{1}".format(port,bit),"INPUT") @@ -100,11 +99,8 @@ class bank(design.design): self.add_pin("p_en_bar{0}".format(port), "INPUT") for port in self.write_ports: self.add_pin("w_en{0}".format(port), "INPUT") - if (self.word_size != self.write_size): - for bit in range(self.num_wmask): - self.add_pin("bank_wmask{0}_{1}".format(port,bit),"INPUT") - # for bit in range(self.num_wmask): - # self.add_pin("wdriver_sel{0}_{1}".format(port, bit),"INOUT") + for bit in range(self.num_wmasks): + self.add_pin("bank_wmask{0}_{1}".format(port,bit),"INPUT") for port in self.all_ports: self.add_pin("wl_en{0}".format(port), "INPUT") self.add_pin("vdd","POWER") @@ -413,11 +409,8 @@ class bank(design.design): temp.append("p_en_bar{0}".format(port)) if port in self.write_ports: temp.append("w_en{0}".format(port)) - if (self.word_size != self.write_size): - for bit in range(self.num_wmask): - temp.append("bank_wmask{0}_{1}".format(port, bit)) - # for bit in range(self.num_wmask): - # temp.append("wdriver_sel_{0}_{1}".format(port, bit)) + for bit in range(self.num_wmasks): + temp.append("bank_wmask{0}_{1}".format(port, bit)) temp.extend(["vdd","gnd"]) self.connect_inst(temp) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index e2138396..fd7a6b42 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -21,7 +21,7 @@ class control_logic(design.design): Dynamically generated Control logic for the total SRAM circuit. """ - def __init__(self, num_rows, words_per_row, word_size, write_size, sram=None, port_type="rw", name=""): + def __init__(self, num_rows, words_per_row, word_size, sram=None, port_type="rw", name=""): """ Constructor """ name = "control_logic_" + port_type design.design.__init__(self, name) @@ -35,7 +35,6 @@ class control_logic(design.design): self.words_per_row = words_per_row self.word_size = word_size self.port_type = port_type - self.write_size = write_size self.num_cols = word_size*words_per_row self.num_words = num_rows*words_per_row @@ -316,14 +315,8 @@ class control_logic(design.design): else: self.input_list = ["csb"] - # if self.word_size != self.write_size: - # self.input_list = ["wmask"] - if self.port_type == "rw": self.dff_output_list = ["cs_bar", "cs", "we_bar", "we"] - # if self.word_size != self.write_size: - # self.dff_output_list.append("wm_bar") - # self.dff_output_list.append("wm") else: self.dff_output_list = ["cs_bar", "cs"] diff --git a/compiler/modules/multibank.py b/compiler/modules/multibank.py index e99dab93..fd061273 100644 --- a/compiler/modules/multibank.py +++ b/compiler/modules/multibank.py @@ -187,7 +187,7 @@ class multibank(design.design): words_per_row=self.words_per_row) self.add_mod(self.sense_amp_array) - if (self.write_size != self.word_size): + if self.write_size is not None: self.write_mask_driver_array = self.mod_write_mask_driver_array(columns=self.num_cols, word_size=self.word_size, write_size=self.write_size) diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 413922dd..0b2fca51 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -21,8 +21,10 @@ class port_data(design.design): sram_config.set_local_config(self) self.port = port - if (self.word_size != self.write_size): - self.num_wmask = int(self.word_size/self.write_size) + if self.write_size is not None: + self.num_wmasks = int(self.word_size/self.write_size) + else: + self.num_wmasks = 0 if name == "": name = "port_data_{0}".format(self.port) @@ -55,7 +57,7 @@ class port_data(design.design): if self.write_driver_array: self.create_write_driver_array() - if (self.word_size != self.write_size): + if self.write_size is not None: self.create_write_mask_and_array() else: self.write_mask_and_array_inst = None @@ -97,11 +99,8 @@ class port_data(design.design): self.add_pin("p_en_bar", "INPUT") if self.port in self.write_ports: self.add_pin("w_en", "INPUT") - if (self.word_size != self.write_size): - for bit in range(self.num_wmask): - self.add_pin("bank_wmask_{}".format(bit),"INPUT") - # for bit in range(self.num_wmask): - # self.add_pin("wdriver_sel_{}".format(bit), "INOUT") + for bit in range(self.num_wmasks): + self.add_pin("bank_wmask_{}".format(bit),"INPUT") self.add_pin("vdd","POWER") self.add_pin("gnd","GROUND") @@ -177,7 +176,7 @@ class port_data(design.design): word_size=self.word_size, write_size=self.write_size) self.add_mod(self.write_driver_array) - if (self.word_size != self.write_size): + if self.write_size is not None: self.write_mask_and_array = factory.create(module_type="write_mask_and_array", columns=self.num_cols, word_size=self.word_size, @@ -300,7 +299,7 @@ class port_data(design.design): temp.append(self.bl_names[self.port]+"_out_{0}".format(bit)) temp.append(self.br_names[self.port]+"_out_{0}".format(bit)) - if (self.write_size != self.word_size): + if self.write_size is not None: i = 0 for bit in range(0,self.word_size,self.write_size): for x in range(self.write_size): @@ -318,10 +317,10 @@ class port_data(design.design): mod=self.write_mask_and_array) temp = [] - for bit in range(self.num_wmask): + for bit in range(self.num_wmasks): temp.append("bank_wmask_{}".format(bit)) temp.extend(["w_en"]) - for bit in range(self.num_wmask): + for bit in range(self.num_wmasks): temp.append("wdriver_sel_{}".format(bit)) temp.extend(["vdd", "gnd"]) self.connect_inst(temp) diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py index 0a9f0f6b..9e0f992f 100644 --- a/compiler/modules/write_driver_array.py +++ b/compiler/modules/write_driver_array.py @@ -19,7 +19,7 @@ class write_driver_array(design.design): Dynamically generated write driver array of all bitlines. """ - def __init__(self, name, columns, word_size,write_size): + def __init__(self, name, columns, word_size,write_size=None): design.design.__init__(self, name) debug.info(1, "Creating {0}".format(self.name)) self.add_comment("columns: {0}".format(columns)) @@ -60,7 +60,7 @@ class write_driver_array(design.design): for i in range(self.word_size): self.add_pin("bl_{0}".format(i)) self.add_pin("br_{0}".format(i)) - if self.word_size != self.write_size: + if self.write_size != None: for i in range(self.word_size): self.add_pin("en_{}".format(i)) else: @@ -84,7 +84,7 @@ class write_driver_array(design.design): self.driver_insts[index]=self.add_inst(name=name, mod=self.driver) - if self.word_size != self.write_size: + if self.write_size != None: self.connect_inst(["data_{0}".format(index), "bl_{0}".format(index), "br_{0}".format(index), diff --git a/compiler/modules/write_mask_and_array.py b/compiler/modules/write_mask_and_array.py index 04e5e21b..9a9a8f12 100644 --- a/compiler/modules/write_mask_and_array.py +++ b/compiler/modules/write_mask_and_array.py @@ -31,7 +31,7 @@ class write_mask_and_array(design.design): self.word_size = word_size self.write_size = write_size self.words_per_row = int(columns / word_size) - self.num_wmask = int(word_size / write_size) + self.num_wmasks = int(word_size / write_size) self.create_netlist() # if not OPTS.netlist_only: @@ -59,10 +59,10 @@ class write_mask_and_array(design.design): # self.DRC_LVS() def add_pins(self): - for bit in range(self.num_wmask): + for bit in range(self.num_wmasks): self.add_pin("wmask_in_{}".format(bit),"INPUT") self.add_pin("en", "INPUT") - for bit in range(self.num_wmask): + for bit in range(self.num_wmasks): self.add_pin("wmask_out_{}".format(bit),"OUTPUT") self.add_pin("vdd","POWER") self.add_pin("gnd","GROUND") @@ -92,7 +92,7 @@ class write_mask_and_array(design.design): def create_and2_array(self): self.and2_insts = {} - for bit in range(self.num_wmask): + for bit in range(self.num_wmasks): name = "and2_{}".format(bit) self.and2_insts[bit] = self.add_inst(name=name, mod=self.and2) diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index 1d749e16..0ee0bb4f 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -46,7 +46,7 @@ class sram_1bank(sram_base): self.data_dff_insts = self.create_data_dff() - if (self.write_size != self.word_size): + if self.write_size is not None: self.wmask_dff_insts = self.create_wmask_dff() @@ -126,7 +126,7 @@ class sram_1bank(sram_base): self.data_dff_insts[port].place(data_pos[port]) # Add the write mask flops to the left of the din flops. - if (self.write_size != self.word_size): + if self.write_size is not None: if port in self.write_ports: wmask_pos[port] = vector(self.bank.bank_array_ll.x - self.control_logic_insts[port].width, -max_gap_size - self.wmask_dff_insts[port].height) @@ -148,7 +148,7 @@ class sram_1bank(sram_base): self.data_dff_insts[port].place(data_pos[port], mirror="MX") # Add the write mask flops to the left of the din flops. - if (self.write_size != self.word_size): + if self.write_size is not None: if port in self.write_ports: wmask_pos[port] = vector(self.bank.bank_array_ur.x - self.data_dff_insts[port].width, self.bank.height + max_gap_size + self.data_dff_insts[port].height) @@ -362,7 +362,7 @@ class sram_1bank(sram_base): #Data dffs and wmask dffs are only for writing so are not useful for evaluating read delay. for inst in self.data_dff_insts: self.graph_inst_exclude.add(inst) - if (self.write_size != self.word_size): + if self.write_size is not None: for inst in self.wmask_dff_insts: self.graph_inst_exclude.add(inst) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 66dcdb0f..7b7a77f0 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -34,13 +34,18 @@ class sram_base(design, verilog, lef): sram_config.set_local_config(self) self.bank_insts = [] - + + if self.write_size is not None: + self.num_wmasks = int(self.word_size/self.write_size) + else: + self.num_wmasks = 0 + #For logical effort delay calculations. self.all_mods_except_control_done = False def add_pins(self): """ Add pins for entire SRAM. """ - self.num_masks = int(self.word_size/self.write_size) + for port in self.write_ports: for bit in range(self.word_size): self.add_pin("DIN{0}[{1}]".format(port,bit),"INPUT") @@ -70,10 +75,9 @@ class sram_base(design, verilog, lef): for port in self.all_ports: self.add_pin("clk{}".format(port),"INPUT") # add the optional write mask pins - if self.word_size != self.write_size: - for port in self.write_ports: - for bit in range(self.num_masks): - self.add_pin("wmask{0}[{1}]".format(port,bit),"INPUT") + for port in self.write_ports: + for bit in range(self.num_wmasks): + self.add_pin("wmask{0}[{1}]".format(port,bit),"INPUT") for port in self.read_ports: for bit in range(self.word_size): self.add_pin("DOUT{0}[{1}]".format(port,bit),"OUTPUT") @@ -280,9 +284,8 @@ class sram_base(design, verilog, lef): self.data_dff = dff_array(name="data_dff", rows=1, columns=self.word_size) self.add_mod(self.data_dff) - if (self.write_size != self.word_size): - num_wmask = int(self.word_size/self.write_size) - self.wmask_dff = dff_array(name="wmask_dff", rows=1, columns=num_wmask) + if self.write_size is not None: + self.wmask_dff = dff_array(name="wmask_dff", rows=1, columns=self.num_wmasks) self.add_mod(self.wmask_dff) @@ -312,23 +315,20 @@ class sram_base(design, verilog, lef): self.control_logic_rw = self.mod_control_logic(num_rows=self.num_rows, words_per_row=self.words_per_row, word_size=self.word_size, - write_size = self.write_size, - sram=self, + sram=self, port_type="rw") self.add_mod(self.control_logic_rw) if len(self.writeonly_ports)>0: self.control_logic_w = self.mod_control_logic(num_rows=self.num_rows, words_per_row=self.words_per_row, word_size=self.word_size, - write_size=self.write_size, - sram=self, + sram=self, port_type="w") self.add_mod(self.control_logic_w) if len(self.readonly_ports)>0: self.control_logic_r = self.mod_control_logic(num_rows=self.num_rows, words_per_row=self.words_per_row, word_size=self.word_size, - write_size=self.write_size, sram=self, port_type="r") self.add_mod(self.control_logic_r) @@ -357,11 +357,8 @@ class sram_base(design, verilog, lef): temp.append("p_en_bar{0}".format(port)) for port in self.write_ports: temp.append("w_en{0}".format(port)) - if (self.word_size != self.write_size): - for bit in range(self.num_masks): - temp.append("bank_wmask{}[{}]".format(port, bit)) - # for bit in range(self.num_masks): - # temp.append("wdriver_sel{}[{}]".format(port, bit)) + for bit in range(self.num_wmasks): + temp.append("bank_wmask{}[{}]".format(port, bit)) for port in self.all_ports: temp.append("wl_en{0}".format(port)) temp.extend(["vdd", "gnd"]) @@ -463,7 +460,6 @@ class sram_base(design, verilog, lef): def create_wmask_dff(self): """ Add and place all wmask flops """ - num_wmask = int(self.word_size/self.write_size) insts = [] for port in self.all_ports: if port in self.write_ports: @@ -476,7 +472,7 @@ class sram_base(design, verilog, lef): # inputs, outputs/output/bar inputs = [] outputs = [] - for bit in range(num_wmask): + for bit in range(self.num_wmasks): inputs.append("wmask{}[{}]".format(port, bit)) outputs.append("bank_wmask{}[{}]".format(port, bit)) diff --git a/compiler/sram/sram_config.py b/compiler/sram/sram_config.py index 80be7939..df9ae677 100644 --- a/compiler/sram/sram_config.py +++ b/compiler/sram/sram_config.py @@ -23,8 +23,6 @@ class sram_config: # This will get over-written when we determine the organization self.words_per_row = words_per_row - if self.write_size == None: - self.write_size = self.word_size self.compute_sizes() @@ -64,26 +62,7 @@ class sram_config: self.words_per_row = self.amend_words_per_row(self.tentative_num_rows, self.words_per_row) debug.info(1,"Words per row: {}".format(self.words_per_row)) - self.recompute_sizes_once() - - def recompute_sizes_once(self): - """ - Calculate the auxiliary values assuming fixed number of words per row. - """ - - # If the banks changed - self.num_words_per_bank = self.num_words / self.num_banks - self.num_bits_per_bank = self.word_size * self.num_words_per_bank - - # Fix the number of columns and rows - self.num_cols = int(self.words_per_row * self.word_size) - self.num_rows = int(self.num_words_per_bank / self.words_per_row) - - # Compute the address and bank sizes - self.row_addr_size = int(log(self.num_rows, 2)) - self.col_addr_size = int(log(self.words_per_row, 2)) - self.bank_addr_size = self.col_addr_size + self.row_addr_size - self.addr_size = self.bank_addr_size + int(log(self.num_banks, 2)) + self.recompute_sizes() def recompute_sizes(self): """ @@ -92,10 +71,6 @@ class sram_config: SRAM for testing. """ - # This function is ran without the write mask option, but word_size can be redefined - # which makes the tests think there is a write mask. - self.write_size = self.word_size - # If the banks changed self.num_words_per_bank = self.num_words/self.num_banks self.num_bits_per_bank = self.word_size*self.num_words_per_bank diff --git a/compiler/tests/22_sram_wmask_func_test.py b/compiler/tests/22_sram_wmask_func_test.py index f76fdeef..9a7b04fd 100755 --- a/compiler/tests/22_sram_wmask_func_test.py +++ b/compiler/tests/22_sram_wmask_func_test.py @@ -35,7 +35,7 @@ class sram_wmask_func_test(openram_test): write_size=4, num_banks=1) c.words_per_row=1 - c.recompute_sizes_once() + c.recompute_sizes() debug.info(1, "Functional test for sram with {} bit words, {} words, {} words per row, {} bit writes, {} banks".format(c.word_size, c.num_words, c.words_per_row,