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Change num_wmask to num_wmasks and write_size = None not word_size if wmask not used.

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jsowash
2019-07-19 14:58:37 -07:00
parent 45cb159d7f
commit 0a5461201a
13 changed files with 91 additions and 138 deletions
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compiler/modules/bank.py
+8 -15
View File
@@ -30,8 +30,10 @@ class bank(design.design):
self.sram_config = sram_config
sram_config.set_local_config(self)
if (self.word_size != self.write_size):
self.num_wmask = int(self.word_size/self.write_size)
if self.write_size is not None:
self.num_wmasks = int(self.word_size/self.write_size)
else:
self.num_wmasks = 0
if name == "":
name = "bank_{0}_{1}".format(self.word_size, self.num_words)
@@ -82,9 +84,6 @@ class bank(design.design):
for port in self.write_ports:
for bit in range(self.word_size):
self.add_pin("din{0}_{1}".format(port,bit),"IN")
# if (self.word_size != self.write_size):
# for bit in range(self.word_size):
# self.add_pin()
for port in self.all_ports:
for bit in range(self.addr_size):
self.add_pin("addr{0}_{1}".format(port,bit),"INPUT")
@@ -100,11 +99,8 @@ class bank(design.design):
self.add_pin("p_en_bar{0}".format(port), "INPUT")
for port in self.write_ports:
self.add_pin("w_en{0}".format(port), "INPUT")
if (self.word_size != self.write_size):
for bit in range(self.num_wmask):
self.add_pin("bank_wmask{0}_{1}".format(port,bit),"INPUT")
# for bit in range(self.num_wmask):
# self.add_pin("wdriver_sel{0}_{1}".format(port, bit),"INOUT")
for bit in range(self.num_wmasks):
self.add_pin("bank_wmask{0}_{1}".format(port,bit),"INPUT")
for port in self.all_ports:
self.add_pin("wl_en{0}".format(port), "INPUT")
self.add_pin("vdd","POWER")
@@ -413,11 +409,8 @@ class bank(design.design):
temp.append("p_en_bar{0}".format(port))
if port in self.write_ports:
temp.append("w_en{0}".format(port))
if (self.word_size != self.write_size):
for bit in range(self.num_wmask):
temp.append("bank_wmask{0}_{1}".format(port, bit))
# for bit in range(self.num_wmask):
# temp.append("wdriver_sel_{0}_{1}".format(port, bit))
for bit in range(self.num_wmasks):
temp.append("bank_wmask{0}_{1}".format(port, bit))
temp.extend(["vdd","gnd"])
self.connect_inst(temp)
compiler/modules/control_logic.py
+1 -8
View File
@@ -21,7 +21,7 @@ class control_logic(design.design):
Dynamically generated Control logic for the total SRAM circuit.
"""
def __init__(self, num_rows, words_per_row, word_size, write_size, sram=None, port_type="rw", name=""):
def __init__(self, num_rows, words_per_row, word_size, sram=None, port_type="rw", name=""):
""" Constructor """
name = "control_logic_" + port_type
design.design.__init__(self, name)
@@ -35,7 +35,6 @@ class control_logic(design.design):
self.words_per_row = words_per_row
self.word_size = word_size
self.port_type = port_type
self.write_size = write_size
self.num_cols = word_size*words_per_row
self.num_words = num_rows*words_per_row
@@ -316,14 +315,8 @@ class control_logic(design.design):
else:
self.input_list = ["csb"]
# if self.word_size != self.write_size:
# self.input_list = ["wmask"]
if self.port_type == "rw":
self.dff_output_list = ["cs_bar", "cs", "we_bar", "we"]
# if self.word_size != self.write_size:
# self.dff_output_list.append("wm_bar")
# self.dff_output_list.append("wm")
else:
self.dff_output_list = ["cs_bar", "cs"]
compiler/modules/multibank.py
+1 -1
View File
@@ -187,7 +187,7 @@ class multibank(design.design):
words_per_row=self.words_per_row)
self.add_mod(self.sense_amp_array)
if (self.write_size != self.word_size):
if self.write_size is not None:
self.write_mask_driver_array = self.mod_write_mask_driver_array(columns=self.num_cols,
word_size=self.word_size,
write_size=self.write_size)
compiler/modules/port_data.py
+11 -12
View File
@@ -21,8 +21,10 @@ class port_data(design.design):
sram_config.set_local_config(self)
self.port = port
if (self.word_size != self.write_size):
self.num_wmask = int(self.word_size/self.write_size)
if self.write_size is not None:
self.num_wmasks = int(self.word_size/self.write_size)
else:
self.num_wmasks = 0
if name == "":
name = "port_data_{0}".format(self.port)
@@ -55,7 +57,7 @@ class port_data(design.design):
if self.write_driver_array:
self.create_write_driver_array()
if (self.word_size != self.write_size):
if self.write_size is not None:
self.create_write_mask_and_array()
else:
self.write_mask_and_array_inst = None
@@ -97,11 +99,8 @@ class port_data(design.design):
self.add_pin("p_en_bar", "INPUT")
if self.port in self.write_ports:
self.add_pin("w_en", "INPUT")
if (self.word_size != self.write_size):
for bit in range(self.num_wmask):
self.add_pin("bank_wmask_{}".format(bit),"INPUT")
# for bit in range(self.num_wmask):
# self.add_pin("wdriver_sel_{}".format(bit), "INOUT")
for bit in range(self.num_wmasks):
self.add_pin("bank_wmask_{}".format(bit),"INPUT")
self.add_pin("vdd","POWER")
self.add_pin("gnd","GROUND")
@@ -177,7 +176,7 @@ class port_data(design.design):
word_size=self.word_size,
write_size=self.write_size)
self.add_mod(self.write_driver_array)
if (self.word_size != self.write_size):
if self.write_size is not None:
self.write_mask_and_array = factory.create(module_type="write_mask_and_array",
columns=self.num_cols,
word_size=self.word_size,
@@ -300,7 +299,7 @@ class port_data(design.design):
temp.append(self.bl_names[self.port]+"_out_{0}".format(bit))
temp.append(self.br_names[self.port]+"_out_{0}".format(bit))
if (self.write_size != self.word_size):
if self.write_size is not None:
i = 0
for bit in range(0,self.word_size,self.write_size):
for x in range(self.write_size):
@@ -318,10 +317,10 @@ class port_data(design.design):
mod=self.write_mask_and_array)
temp = []
for bit in range(self.num_wmask):
for bit in range(self.num_wmasks):
temp.append("bank_wmask_{}".format(bit))
temp.extend(["w_en"])
for bit in range(self.num_wmask):
for bit in range(self.num_wmasks):
temp.append("wdriver_sel_{}".format(bit))
temp.extend(["vdd", "gnd"])
self.connect_inst(temp)
compiler/modules/write_driver_array.py
+3 -3
View File
@@ -19,7 +19,7 @@ class write_driver_array(design.design):
Dynamically generated write driver array of all bitlines.
"""
def __init__(self, name, columns, word_size,write_size):
def __init__(self, name, columns, word_size,write_size=None):
design.design.__init__(self, name)
debug.info(1, "Creating {0}".format(self.name))
self.add_comment("columns: {0}".format(columns))
@@ -60,7 +60,7 @@ class write_driver_array(design.design):
for i in range(self.word_size):
self.add_pin("bl_{0}".format(i))
self.add_pin("br_{0}".format(i))
if self.word_size != self.write_size:
if self.write_size != None:
for i in range(self.word_size):
self.add_pin("en_{}".format(i))
else:
@@ -84,7 +84,7 @@ class write_driver_array(design.design):
self.driver_insts[index]=self.add_inst(name=name,
mod=self.driver)
if self.word_size != self.write_size:
if self.write_size != None:
self.connect_inst(["data_{0}".format(index),
"bl_{0}".format(index),
"br_{0}".format(index),
compiler/modules/write_mask_and_array.py
+4 -4
View File
@@ -31,7 +31,7 @@ class write_mask_and_array(design.design):
self.word_size = word_size
self.write_size = write_size
self.words_per_row = int(columns / word_size)
self.num_wmask = int(word_size / write_size)
self.num_wmasks = int(word_size / write_size)
self.create_netlist()
# if not OPTS.netlist_only:
@@ -59,10 +59,10 @@ class write_mask_and_array(design.design):
# self.DRC_LVS()
def add_pins(self):
for bit in range(self.num_wmask):
for bit in range(self.num_wmasks):
self.add_pin("wmask_in_{}".format(bit),"INPUT")
self.add_pin("en", "INPUT")
for bit in range(self.num_wmask):
for bit in range(self.num_wmasks):
self.add_pin("wmask_out_{}".format(bit),"OUTPUT")
self.add_pin("vdd","POWER")
self.add_pin("gnd","GROUND")
@@ -92,7 +92,7 @@ class write_mask_and_array(design.design):
def create_and2_array(self):
self.and2_insts = {}
for bit in range(self.num_wmask):
for bit in range(self.num_wmasks):
name = "and2_{}".format(bit)
self.and2_insts[bit] = self.add_inst(name=name,
mod=self.and2)