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https://github.com/VLSIDA/OpenRAM.git
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Change num_wmask to num_wmasks and write_size = None not word_size if wmask not used.
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@@ -34,10 +34,11 @@ class simulation():
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self.readwrite_ports = self.sram.readwrite_ports
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self.read_ports = self.sram.read_ports
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self.write_ports = self.sram.write_ports
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self.num_wmask = int(self.word_size/self.write_size)
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self.wmask_enabled = False
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if self.word_size !=self.write_size:
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self.wmask_enabled = True
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if self.write_size is not None:
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self.num_wmasks = int(self.word_size/self.write_size)
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else:
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self.num_wmasks = 0
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def set_corner(self,corner):
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""" Set the corner values """
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@@ -79,7 +80,7 @@ class simulation():
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# Three dimensional list to handle each addr and data bits for wach port over the number of checks
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self.addr_values = [[[] for bit in range(self.addr_size)] for port in self.all_ports]
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self.data_values = [[[] for bit in range(self.word_size)] for port in self.write_ports]
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self.wmask_values = [[[] for bit in range(self.num_wmask)] for port in self.write_ports]
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self.wmask_values = [[[] for bit in range(self.num_wmasks)] for port in self.write_ports]
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# For generating comments in SPICE stimulus
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self.cycle_comments = []
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@@ -248,7 +249,7 @@ class simulation():
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t_current,
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t_current+self.period)
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elif op == "write":
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if (self.wmask_enabled):
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if self.write_size is not None:
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comment = "\tWriting {0} to address {1} with mask bit {2} (from port {3}) during cycle {4} ({5}ns - {6}ns)".format(word,
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addr,
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wmask,
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@@ -300,9 +301,8 @@ class simulation():
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for port in range(total_ports):
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pin_names.append("{0}{1}".format(tech.spice["clk"], port))
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if (self.write_size != self.word_size):
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num_wmask = int(self.word_size/self.write_size)
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for bit in range(num_wmask):
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if self.write_size is not None:
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for bit in range(self.num_wmasks):
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pin_names.append("WMASK{0}_{1}".format(port,bit))
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for read_output in read_index:
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