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Change num_wmask to num_wmasks and write_size = None not word_size if wmask not used.

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jsowash
2019-07-19 14:58:37 -07:00
parent 45cb159d7f
commit 0a5461201a
13 changed files with 91 additions and 138 deletions
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compiler/characterizer/functional.py
+13 -12
View File
@@ -32,6 +32,11 @@ class functional(simulation):
if OPTS.is_unit_test:
random.seed(12345)
if self.write_size is not None:
self.num_wmasks = int(self.word_size / self.write_size)
else:
self.num_wmasks = 0
self.set_corner(corner)
self.set_spice_constants()
#self.set_feasible_period(sram, spfile, corner)
@@ -46,13 +51,10 @@ class functional(simulation):
self.read_check = []
def initilize_wmask(self):
self.wmask = [None]*self.num_wmask
self.num_wmask = int(self.word_size/self.write_size)
self.wmask_enabled = False
if self.word_size !=self.write_size:
self.wmask_enabled = True
self.wmask = [None]*self.num_wmasks
if self.write_size is not None:
# initialize wmask to 1
for bit in range(self.num_wmask):
for bit in range(self.num_wmasks):
self.wmask[bit] = 1
# if bit == 0:
# self.wmask[self.num_wmask-1 - bit] = 1
@@ -189,8 +191,8 @@ class functional(simulation):
return(1, "SUCCESS")
def gen_wmask(self):
wmask_bits = [None]*self.num_wmask
for bit in range(self.num_wmask):
wmask_bits = [None]*self.num_wmasks
for bit in range(self.num_wmasks):
rand = random.randint(0, 1)
wmask_bits[bit] = rand
return wmask_bits
@@ -292,10 +294,9 @@ class functional(simulation):
# Generate wmask bits
for port in self.write_ports:
self.sf.write("\n* Generation of wmask signals\n")
if (self.write_size != self.word_size):
num_wmask = int(self.word_size / self.write_size)
for bit in range(num_wmask):
self.sf.write("\n* Generation of wmask sibfssgnals\n")
if self.write_size is not None:
for bit in range(self.num_wmasks):
sig_name = "WMASK{0}_{1} ".format(port, bit)
self.stim.gen_pwl(sig_name, self.cycle_times, self.data_values[port][bit], self.period,
self.slew, 0.05)
compiler/characterizer/simulation.py
+9 -9
View File
@@ -34,10 +34,11 @@ class simulation():
self.readwrite_ports = self.sram.readwrite_ports
self.read_ports = self.sram.read_ports
self.write_ports = self.sram.write_ports
self.num_wmask = int(self.word_size/self.write_size)
self.wmask_enabled = False
if self.word_size !=self.write_size:
self.wmask_enabled = True
if self.write_size is not None:
self.num_wmasks = int(self.word_size/self.write_size)
else:
self.num_wmasks = 0
def set_corner(self,corner):
""" Set the corner values """
@@ -79,7 +80,7 @@ class simulation():
# Three dimensional list to handle each addr and data bits for wach port over the number of checks
self.addr_values = [[[] for bit in range(self.addr_size)] for port in self.all_ports]
self.data_values = [[[] for bit in range(self.word_size)] for port in self.write_ports]
self.wmask_values = [[[] for bit in range(self.num_wmask)] for port in self.write_ports]
self.wmask_values = [[[] for bit in range(self.num_wmasks)] for port in self.write_ports]
# For generating comments in SPICE stimulus
self.cycle_comments = []
@@ -248,7 +249,7 @@ class simulation():
t_current,
t_current+self.period)
elif op == "write":
if (self.wmask_enabled):
if self.write_size is not None:
comment = "\tWriting {0} to address {1} with mask bit {2} (from port {3}) during cycle {4} ({5}ns - {6}ns)".format(word,
addr,
wmask,
@@ -300,9 +301,8 @@ class simulation():
for port in range(total_ports):
pin_names.append("{0}{1}".format(tech.spice["clk"], port))
if (self.write_size != self.word_size):
num_wmask = int(self.word_size/self.write_size)
for bit in range(num_wmask):
if self.write_size is not None:
for bit in range(self.num_wmasks):
pin_names.append("WMASK{0}_{1}".format(port,bit))
for read_output in read_index: