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Attempts to fix failing tests. Random seed differences between mada and pipeline.

This commit is contained in:
Hunter Nichols 2018-12-12 13:12:26 -08:00
parent 6ac474d642
commit 0a26e40022
2 changed files with 4 additions and 3 deletions
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6
compiler/modules/control_logic.py
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@ -135,10 +135,10 @@ class control_logic(design.design):
# FIXME: These should be tuned according to the additional size parameters # FIXME: These should be tuned according to the additional size parameters
delay_fanout = 3 # This can be anything >=2 delay_fanout = 3 # This can be anything >=2
# Delay stages Must be non-inverting # Delay stages Must be non-inverting
if self.words_per_row >= 8: if self.words_per_row >= 4:
delay_stages = 8
elif self.words_per_row == 4:
delay_stages = 8 delay_stages = 8
elif self.words_per_row == 2:
delay_stages = 6
else: else:
delay_stages = 4 delay_stages = 4

1
compiler/tests/21_hspice_delay_test.py
View File

@ -29,6 +29,7 @@ class timing_sram_test(openram_test):
c = sram_config(word_size=1, c = sram_config(word_size=1,
num_words=16, num_words=16,
num_banks=1) num_banks=1)
c.words_per_row=1
debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank") debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram(c, name="sram1") s = sram(c, name="sram1")