diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py
index daa0358f..c30d91a0 100644
--- a/compiler/modules/control_logic.py
+++ b/compiler/modules/control_logic.py
@@ -135,10 +135,10 @@ class control_logic(design.design):
         # FIXME: These should be tuned according to the additional size parameters
         delay_fanout = 3 # This can be anything >=2
         # Delay stages Must be non-inverting
-        if self.words_per_row >= 8:
-            delay_stages = 8
-        elif self.words_per_row == 4:
+        if self.words_per_row >= 4:
             delay_stages = 8
+        elif self.words_per_row == 2:
+            delay_stages = 6
         else:
             delay_stages = 4
             
diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py
index 53b089f9..143b29b8 100755
--- a/compiler/tests/21_hspice_delay_test.py
+++ b/compiler/tests/21_hspice_delay_test.py
@@ -29,6 +29,7 @@ class timing_sram_test(openram_test):
         c = sram_config(word_size=1,
                         num_words=16,
                         num_banks=1)
+        c.words_per_row=1
         debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
         s = sram(c, name="sram1")