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Change path to wire_path for Anaconda package conflict
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@@ -13,7 +13,7 @@ class path_test(openram_test):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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import path
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import wire_path
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import tech
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import design
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@@ -27,7 +27,7 @@ class path_test(openram_test):
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[0, 3 * min_space ],
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[0, 6 * min_space ]]
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w = design.design("path_test0")
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path.path(w,layer_stack, position_list)
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wire_path.wire_path(w,layer_stack, position_list)
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self.local_drc_check(w)
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@@ -44,7 +44,7 @@ class path_test(openram_test):
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[-1 * min_space, 0]]
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position_list = [[x+min_space, y+min_space] for x,y in old_position_list]
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w = design.design("path_test1")
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path.path(w,layer_stack, position_list)
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wire_path.wire_path(w,layer_stack, position_list)
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self.local_drc_check(w)
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min_space = 2 * tech.drc["minwidth_metal2"]
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@@ -60,7 +60,7 @@ class path_test(openram_test):
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[-1 * min_space, 0]]
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position_list = [[x-min_space, y-min_space] for x,y in old_position_list]
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w = design.design("path_test2")
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path.path(w, layer_stack, position_list)
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wire_path.wire_path(w, layer_stack, position_list)
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self.local_drc_check(w)
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min_space = 2 * tech.drc["minwidth_metal3"]
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@@ -77,7 +77,7 @@ class path_test(openram_test):
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# run on the reverse list
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position_list.reverse()
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w = design.design("path_test3")
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path.path(w, layer_stack, position_list)
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wire_path.wire_path(w, layer_stack, position_list)
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self.local_drc_check(w)
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globals.end_openram()
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