Fix base bitcell syntax error. Remove some unused imports.

This commit is contained in:
mrg
2020-01-30 01:58:30 +00:00
parent 79391b84da
commit 0880c393fd
2 changed files with 3 additions and 11 deletions
+2 -7
View File
@@ -3,15 +3,11 @@
# Copyright (c) 2016-2019 Regents of the University of California
# All rights reserved.
#
import debug
import design
from base_array import bitcell_base_array
from tech import drc
import contact
from bitcell_base_array import bitcell_base_array
from sram_factory import factory
from vector import vector
from globals import OPTS
class dummy_array(bitcell_base_array):
"""
Generate a dummy row/column for the replica array.
@@ -23,7 +19,6 @@ class dummy_array(bitcell_base_array):
self.create_netlist()
if not OPTS.netlist_only:
self.create_layout()
def create_netlist(self):
""" Create and connect the netlist """