diff --git a/compiler/modules/dummy_array.py b/compiler/modules/dummy_array.py
index 997330e1..de15d0ce 100644
--- a/compiler/modules/dummy_array.py
+++ b/compiler/modules/dummy_array.py
@@ -3,15 +3,11 @@
 # Copyright (c) 2016-2019 Regents of the University of California 
 # All rights reserved.
 #
-import debug
-import design
-from base_array import bitcell_base_array
-from tech import drc
-import contact
+from bitcell_base_array import bitcell_base_array
 from sram_factory import factory
-from vector import vector
 from globals import OPTS
 
+
 class dummy_array(bitcell_base_array):
     """
     Generate a dummy row/column for the replica array.
@@ -23,7 +19,6 @@ class dummy_array(bitcell_base_array):
         self.create_netlist()
         if not OPTS.netlist_only:
             self.create_layout()
-
         
     def create_netlist(self):
         """ Create and connect the netlist """
diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py
index 9cf5c5a2..178c2f91 100644
--- a/compiler/modules/replica_bitcell_array.py
+++ b/compiler/modules/replica_bitcell_array.py
@@ -10,10 +10,7 @@ from tech import drc, spice
 from vector import vector
 from globals import OPTS
 from sram_factory import factory
-import logical_effort
-import bitcell_array
-import replica_column
-import dummy_array
+
 
 class replica_bitcell_array(design.design):
     """