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Temporarily made the functional tests write/read only all 0's or 1's

This commit is contained in:
jsowash 2019-07-18 15:26:38 -07:00
parent 5f37067da7
commit 082decba18
3 changed files with 46 additions and 55 deletions
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55
compiler/characterizer/functional.py
View File

@ -51,12 +51,13 @@ class functional(simulation):
self.wmask_enabled = False self.wmask_enabled = False
if self.word_size !=self.write_size: if self.word_size !=self.write_size:
self.wmask_enabled = True self.wmask_enabled = True
# initialize first wmask bit to 1, otherwise 0 # initialize wmask to 1
for bit in range(self.num_wmask): for bit in range(self.num_wmask):
if bit == 0: self.wmask[bit] = 1
self.wmask[self.num_wmask-1 - bit] = 1 # if bit == 0:
else: # self.wmask[self.num_wmask-1 - bit] = 1
self.wmask[self.num_wmask-1 - bit] = 0 # else:
# self.wmask[self.num_wmask-1 - bit] = 0
def run(self, feasible_period=None): def run(self, feasible_period=None):
if feasible_period: #period defaults to tech.py feasible period otherwise. if feasible_period: #period defaults to tech.py feasible period otherwise.
@ -92,28 +93,7 @@ class functional(simulation):
word = self.gen_data() word = self.gen_data()
comment = self.gen_cycle_comment("write", word, addr, 0, self.wmask, self.t_current) comment = self.gen_cycle_comment("write", word, addr, 0, self.wmask, self.t_current)
self.add_write(comment, addr, word, 0) self.add_write(comment, addr, word, 0)
if self.wmask_enabled: self.stored_words[addr] = word
old_word = ""
if self.stored_words.get(addr) == None:
for i in range(self.word_size):
old_word += "X"
else:
old_word = self.stored_words[addr]
for bit in self.wmask:
# Don't write the bits of the new word to the address
if self.wmask[bit] == 0:
lower = bit * self.write_size
upper = lower + self.write_size - 1
if bit == self.num_wmask-1:
word = word[0:lower] + old_word[lower:upper+1]
elif bit == 0:
word = old_word[lower:upper+1] + word [upper+1:self.word_size]
else:
word = word[0:lower] + old_word[lower:upper+1] + word [upper+1:self.word_size]
#word = word.replace(word[lower:upper+1],old_word[lower:upper+1],1)
self.stored_words[addr] = word
else:
self.stored_words[addr] = word
# Read at least once. For multiport, it is important that one read cycle uses all RW and R port to read from the same address simultaniously. # Read at least once. For multiport, it is important that one read cycle uses all RW and R port to read from the same address simultaniously.
# This will test the viablilty of the transistor sizing in the bitcell. # This will test the viablilty of the transistor sizing in the bitcell.
@ -124,7 +104,6 @@ class functional(simulation):
comment = self.gen_cycle_comment("read", word, addr, port, self.wmask, self.t_current) comment = self.gen_cycle_comment("read", word, addr, port, self.wmask, self.t_current)
self.add_read_one_port(comment, addr, rw_read_din_data, port) self.add_read_one_port(comment, addr, rw_read_din_data, port)
self.write_check.append([word, "{0}{1}".format(self.dout_name,port), self.t_current+self.period, check]) self.write_check.append([word, "{0}{1}".format(self.dout_name,port), self.t_current+self.period, check])
# don't check X's
check += 1 check += 1
self.cycle_times.append(self.t_current) self.cycle_times.append(self.t_current)
self.t_current += self.period self.t_current += self.period
@ -148,12 +127,13 @@ class functional(simulation):
elif op == "write": elif op == "write":
addr = self.gen_addr() addr = self.gen_addr()
word = self.gen_data() word = self.gen_data()
wmask = self.gen_wmask() # wmask = self.gen_wmask()
# two ports cannot write to the same address # two ports cannot write to the same address
if addr in w_addrs: if addr in w_addrs:
self.add_noop_one_port("0"*self.addr_size, "0"*self.word_size, port) self.add_noop_one_port("0"*self.addr_size, "0"*self.word_size, port)
else: else:
comment = self.gen_cycle_comment("write", word, addr, port, wmask, self.t_current) # comment = self.gen_cycle_comment("write", word, addr, port, wmask, self.t_current)
comment = self.gen_cycle_comment("read", word, addr, port, self.wmask, self.t_current)
self.add_write_one_port(comment, addr, word, port) self.add_write_one_port(comment, addr, word, port)
self.stored_words[addr] = word self.stored_words[addr] = word
w_addrs.append(addr) w_addrs.append(addr)
@ -215,10 +195,19 @@ class functional(simulation):
wmask_bits[bit] = rand wmask_bits[bit] = rand
return wmask_bits return wmask_bits
# def gen_data(self):
# """ Generates a random word to write. """
# rand = random.randint(0,(2**self.word_size)-1)
# data_bits = self.convert_to_bin(rand,False)
# return data_bits
def gen_data(self): def gen_data(self):
""" Generates a random word to write. """ """ Generates a random word, either all 0 or all 1's, to write. """
rand = random.randint(0,(2**self.word_size)-1) rand = random.randint(0,1)
data_bits = self.convert_to_bin(rand,False) bits = []
for bit in range(self.word_size):
bits.append(rand)
data_bits = ''.join(map(str,bits))
return data_bits return data_bits
def gen_addr(self): def gen_addr(self):

6
compiler/characterizer/simulation.py
View File

@ -234,12 +234,12 @@ class simulation():
t_current+self.period) t_current+self.period)
elif op == "write": elif op == "write":
if (self.wmask_enabled): if (self.wmask_enabled):
comment = "\tWriting {0} to address {1} with mask bit {0} (from port {2}) during cycle {3} ({4}ns - {5}ns)".format(word, comment = "\tWriting {0} to address {1} with mask bit {2} (from port {3}) during cycle {4} ({5}ns - {6}ns)".format(word,
addr, addr,
wmask, wmask,
port, port,
int( int(t_current / self.period),
t_current / self.period), t_current,
t_current + self.period) t_current + self.period)
else: else:

34
compiler/modules/port_data.py
View File

@ -55,12 +55,12 @@ class port_data(design.design):
if self.write_driver_array: if self.write_driver_array:
self.create_write_driver_array() self.create_write_driver_array()
if (self.word_size != self.write_size): if (self.word_size != self.write_size):
self.create_write_mask_array() self.create_write_mask_and_array()
else: else:
self.write_mask_array_inst = None self.write_mask_and_array_inst = None
else: else:
self.write_driver_array_inst = None self.write_driver_array_inst = None
self.write_mask_array_inst = None self.write_mask_and_array_inst = None
if self.column_mux_array: if self.column_mux_array:
self.create_column_mux_array() self.create_column_mux_array()
@ -171,17 +171,17 @@ class port_data(design.design):
word_size=self.word_size) word_size=self.word_size)
self.add_mod(self.write_driver_array) self.add_mod(self.write_driver_array)
if (self.word_size != self.write_size): if (self.word_size != self.write_size):
self.write_mask_array = factory.create(module_type="write_mask_array", self.write_mask_and_array = factory.create(module_type="write_mask_and_array",
columns=self.num_cols, columns=self.num_cols,
word_size=self.word_size, word_size=self.word_size,
write_size=self.write_size) write_size=self.write_size)
self.add_mod(self.write_mask_array) self.add_mod(self.write_mask_and_array)
else: else:
self.write_mask_array_inst = None self.write_mask_and_array_inst = None
else: else:
self.write_driver_array = None self.write_driver_array = None
self.write_mask_array = None self.write_mask_and_array = None
def precompute_constants(self): def precompute_constants(self):
""" Get some preliminary data ready """ """ Get some preliminary data ready """
@ -282,8 +282,10 @@ class port_data(design.design):
mod=self.write_driver_array) mod=self.write_driver_array)
temp = [] temp = []
for bit in range(self.word_size): m
temp.append("din_{}".format(bit)) for bit in range(self.word_size):
temp.append("din_{}".format(bit))
for bit in range(self.word_size): for bit in range(self.word_size):
if (self.words_per_row == 1): if (self.words_per_row == 1):
temp.append(self.bl_names[self.port]+"_{0}".format(bit)) temp.append(self.bl_names[self.port]+"_{0}".format(bit))
@ -295,14 +297,14 @@ class port_data(design.design):
self.connect_inst(temp) self.connect_inst(temp)
def create_write_mask_array(self): def create_write_mask_and_array(self):
""" Creating Write Masks """ """ Creating Write Masks """
self.write_mask_array_inst = self.add_inst(name="write_mask_array{}".format(self.port), self.write_mask_and_array_inst = self.add_inst(name="write_mask_and_array{}".format(self.port),
mod=self.write_mask_array) mod=self.write_mask_and_array)
temp = [] temp = []
for bit in range(self.num_wmask): for bit in range(self.num_wmask):
temp.append("write_mask_".format(bit)) temp.append("write_mask_{}".format(bit))
temp.extend(["w_en", "vdd", "gnd"]) temp.extend(["w_en", "vdd", "gnd"])
self.connect_inst(temp) self.connect_inst(temp)