Add new DFF. Create DFF module. Start dff_array, not tested.

compiler/modules/dff.py

@@ -0,0 +1,29 @@
+import globals
+import design
+from math import log
+import design
+from tech import GDS,layer
+import utils
+
+class dff(design.design):
+    """
+    Memory address flip-flop
+    """
+
+    pin_names = ["d", "clk", "q", "vdd", "gnd"]
+    (width,height) = utils.get_libcell_size("dff", GDS["unit"], layer["boundary"])
+    pin_map = utils.get_libcell_pins(pin_names, "dff", GDS["unit"], layer["boundary"])
+    
+    def __init__(self, name="dff"):
+        design.design.__init__(self, name)
+
+        self.width = dff.width
+        self.height = dff.height
+        self.pin_map = dff.pin_map
+    
+    def analytical_delay(self, slew, load = 0.0):
+        # dont know how to calculate this now, use constant in tech file
+        from tech import spice
+        result = self.return_delay(spice["dff_delay"], spice["dff_slew"])
+        return result
+

compiler/modules/dff_array.py

@@ -0,0 +1,138 @@
+import debug
+import design
+from tech import drc
+from math import log
+from vector import vector
+from globals import OPTS
+
+class dff_array(design.design):
+    """
+    This is a simple row (or multiple rows) of flops.
+    Unlike the data flops, these are never spaced out.
+    """
+
+    def __init__(self, rows, columns, name=""):
+        self.rows = rows
+        self.columns = columns
+
+        if name=="":
+            name = "dff_array_c{0}_w{1}".format(columns,word_size)
+        design.design.__init__(self, name)
+        debug.info(1, "Creating {}".format(self.name))
+
+        c = reload(__import__(OPTS.dff))
+        self.mod_dff = getattr(c, OPTS.dff)
+        self.ms = self.mod_dff("dff")
+        self.add_mod(self.ms)
+
+        self.width = self.columns * self.ms.width
+        self.height = self.rows * self.ms.height
+
+        self.create_layout()
+
+    def create_layout(self):
+        self.add_pins()
+        self.create_dff_array()
+        self.add_layout_pins()
+        self.DRC_LVS()
+
+    def add_pins(self):
+        for row in range(self.rows):  
+            for col in range(self.columns):
+                self.add_pin("din[{0}][{1}]".format(row,col))
+        for row in range(self.rows):  
+            for col in range(self.columns):
+                self.add_pin("dout[{0}][{1}]".format(row,col))
+                #self.add_pin("dout_bar[{0}]".format(i))
+        self.add_pin("clk")
+        self.add_pin("vdd")
+        self.add_pin("gnd")
+
+    def create_dff_array(self):
+        self.ms_inst={}
+        for row in range(self.rows):  
+            for col in range(self.columns):
+                name = "Xdff_r{0}_c{1}".format(row,col)
+            if (row % 2 == 0):
+                base = vector(i*self.ms.width,0)
+                mirror = "R0"
+            else:
+                base = vector((i+1)*self.ms.width,0)
+                mirror = "MY"
+            self.ms_inst[row,col]=self.add_inst(name=name,
+                                                mod=self.ms,
+                                                offset=base, 
+                                                mirror=mirror)
+            self.connect_inst(["din[{0}][{1}]".format(row,col),
+                               "dout[{0}][{1}]".format(row,col),
+                               "clk",
+                               "vdd",
+                               "gnd"])
+
+    def add_layout_pins(self):
+        
+        for i in range(self.word_size):
+
+            for gnd_pin in self.ms_inst[i].get_pins("gnd"):
+                if gnd_pin.layer!="metal2":
+                    continue
+                self.add_layout_pin(text="gnd",
+                                    layer="metal2",
+                                    offset=gnd_pin.ll(),
+                                    width=gnd_pin.width(),
+                                    height=gnd_pin.height())
+
+            din_pins = self.ms_inst[i].get_pins("din")
+            for din_pin in din_pins:
+                self.add_layout_pin(text="din[{}]".format(i),
+                                    layer=din_pin.layer,
+                                    offset=din_pin.ll(),
+                                    width=din_pin.width(),
+                                    height=din_pin.height())
+
+            dout_pin = self.ms_inst[i].get_pin("dout")
+            self.add_layout_pin(text="dout[{}]".format(i),
+                                layer="metal2",
+                                offset=dout_pin.ll(),
+                                width=dout_pin.width(),
+                                height=dout_pin.height())
+
+            doutbar_pin = self.ms_inst[i].get_pin("dout_bar")
+            self.add_layout_pin(text="dout_bar[{}]".format(i),
+                                layer="metal2",
+                                offset=doutbar_pin.ll(),
+                                width=doutbar_pin.width(),
+                                height=doutbar_pin.height())
+            
+            
+        # Continous clk rail along with label.
+        self.add_layout_pin(text="clk",
+                            layer="metal1",
+                            offset=self.ms_inst[0].get_pin("clk").ll().scale(0,1),
+                            width=self.width,
+                            height=drc["minwidth_metal1"])
+
+        
+        # Continous vdd rail along with label.
+        for vdd_pin in self.ms_inst[i].get_pins("vdd"):
+            if vdd_pin.layer!="metal1":
+                continue
+            self.add_layout_pin(text="vdd",
+                                layer="metal1",
+                                offset=vdd_pin.ll().scale(0,1),
+                                width=self.width,
+                                height=drc["minwidth_metal1"])
+
+        # Continous gnd rail along with label.
+        for gnd_pin in self.ms_inst[i].get_pins("gnd"):
+            if gnd_pin.layer!="metal1":
+                continue
+            self.add_layout_pin(text="gnd",
+                                layer="metal1",
+                                offset=gnd_pin.ll().scale(0,1),
+                                width=self.width,
+                                height=drc["minwidth_metal1"])
+            
+
+    def analytical_delay(self, slew, load=0.0):
+        return self.ms.analytical_delay(slew=slew, load=load)

compiler/options.py

@@ -58,6 +58,8 @@ class options(optparse.Values):
     decoder = "hierarchical_decoder"
     ms_flop = "ms_flop"
     ms_flop_array = "ms_flop_array"
+    dff = "dff"
+    dff_array = "dff_array"
     control_logic = "control_logic"
     bitcell_array = "bitcell_array"
     sense_amp = "sense_amp"

compiler/tests/11_dff_array_test.py

@@ -0,0 +1,40 @@
+#!/usr/bin/env python2.7
+"""
+Run a regresion test on a dff_array.
+"""
+
+import unittest
+from testutils import header,openram_test
+import sys,os
+sys.path.append(os.path.join(sys.path[0],".."))
+import globals
+from globals import OPTS
+import debug
+
+class dff_array_test(openram_test):
+
+    def runTest(self):
+        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        global verify
+        import verify
+        OPTS.check_lvsdrc = False
+
+        import dff_array
+
+        debug.info(2, "Testing dff_array for columns=8, word_size=8")
+        a = dff_array.dff_array(columns=8, word_size=8)
+        self.local_check(a)
+
+        debug.info(2, "Testing dff_array for columns=16, word_size=8")
+        a = dff_array.dff_array(columns=16, word_size=8)
+        self.local_check(a)
+        
+        OPTS.check_lvsdrc = True
+        globals.end_openram()
+
+# instantiate a copdsay of the class to actually run the test
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main()

technology/freepdk45/sp_lib/dff.sp

@@ -0,0 +1,46 @@
+* File: DFFPOSX1.pex.netlist
+* Created: Wed Jan  2 18:36:24 2008
+* Program "Calibre xRC"
+* Version "v2007.2_34.24"
+* 
+.subckt dff d clk q vdd gnd
+* 
+MM21 q a_66_6# gnd gnd NMOS_VTG L=5e-08 W=5e-07
+MM19 a_76_6# a_2_6# a_66_6# gnd NMOS_VTG L=5e-08 W=2.5e-07
+MM20 gnd q a_76_6# gnd NMOS_VTG L=5e-08 W=2.5e-07
+MM18 a_66_6# clk a_61_6# gnd NMOS_VTG L=5e-08 W=2.5e-07
+MM17 a_61_6# a_34_4# gnd gnd NMOS_VTG L=5e-08 W=2.5e-07
+MM10 gnd clk a_2_6# gnd NMOS_VTG L=5e-08 W=5e-07
+MM16 a_34_4# a_22_6# gnd gnd NMOS_VTG L=5e-08 W=2.5e-07
+MM15 gnd a_34_4# a_31_6# gnd NMOS_VTG L=5e-08 W=2.5e-07
+MM14 a_31_6# clk a_22_6# gnd NMOS_VTG L=5e-08 W=2.5e-07
+MM13 a_22_6# a_2_6# a_17_6# gnd NMOS_VTG L=5e-08 W=2.5e-07
+MM12 a_17_6# d gnd gnd NMOS_VTG L=5e-08 W=2.5e-07
+MM11 q a_66_6# vdd vdd PMOS_VTG L=5e-08 W=1e-06
+MM9 vdd q a_76_84# vdd PMOS_VTG L=5e-08 W=2.5e-07
+MM8 a_76_84# clk a_66_6# vdd PMOS_VTG L=5e-08 W=2.5e-07
+MM7 a_66_6# a_2_6# a_61_74# vdd PMOS_VTG L=5e-08 W=5e-07
+MM6 a_61_74# a_34_4# vdd vdd PMOS_VTG L=5e-08 W=5e-07
+MM0 vdd clk a_2_6# vdd PMOS_VTG L=5e-08 W=1e-06
+MM5 a_34_4# a_22_6# vdd vdd PMOS_VTG L=5e-08 W=5e-07
+MM4 vdd a_34_4# a_31_74# vdd PMOS_VTG L=5e-08 W=5e-07
+MM3 a_31_74# a_2_6# a_22_6# vdd PMOS_VTG L=5e-08 W=5e-07
+MM2 a_22_6# clk a_17_74# vdd PMOS_VTG L=5e-08 W=5e-07
+MM1 a_17_74# d vdd vdd PMOS_VTG L=5e-08 W=5e-07
+* c_9 a_66_6# 0 0.271997f
+* c_20 clk 0 0.350944f
+* c_27 q 0 0.202617f
+* c_32 a_76_84# 0 0.0210573f
+* c_38 a_76_6# 0 0.0204911f
+* c_45 a_34_4# 0 0.172306f
+* c_55 a_2_6# 0 0.283119f
+* c_59 a_22_6# 0 0.157312f
+* c_64 d 0 0.0816386f
+* c_73 gnd 0 0.254131f
+* c_81 vdd 0 0.23624f
+*
+*.include "dff.pex.netlist.dff.pxi"
+*
+.ends
+*
+*

technology/freepdk45/tech/tech.py

@@ -274,6 +274,11 @@ spice["msflop_hold"] = 1         # DFF hold time in ps
 spice["msflop_delay"] = 20.5     # DFF Clk-to-q delay in ps
 spice["msflop_slew"] = 13.1      # DFF output slew in ps w/ no load
 spice["msflop_in_cap"] = 0.2091  # Input capacitance of ms_flop (Din) [Femto-farad]
+spice["dff_setup"] = 9        # DFF setup time in ps
+spice["dff_hold"] = 1         # DFF hold time in ps
+spice["dff_delay"] = 20.5     # DFF Clk-to-q delay in ps
+spice["dff_slew"] = 13.1      # DFF output slew in ps w/ no load
+spice["dff_in_cap"] = 0.2091  # Input capacitance of ms_flop (Din) [Femto-farad]
 
 
 ###################################################

technology/scn3me_subm/mag_lib/dff.mag

@@ -0,0 +1,293 @@
+magic
+tech scmos
+timestamp 1090351116
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technology/scn3me_subm/sp_lib/dff.sp

@@ -0,0 +1,47 @@
+* Positive edge-triggered FF
+.subckt dff d q clk vdd gnd
+M0 vdd clk a_2_6# vdd p w=12u l=0.6u
++ ad=0p pd=0u as=0p ps=0u 
+M1 a_17_74# d vdd vdd p w=6u l=0.6u
++ ad=0p pd=0u as=0p ps=0u 
+M2 a_22_6# clk a_17_74# vdd p w=6u l=0.6u
++ ad=0p pd=0u as=0p ps=0u 
+M3 a_31_74# a_2_6# a_22_6# vdd p w=6u l=0.6u
++ ad=0p pd=0u as=0p ps=0u 
+M4 vdd a_34_4# a_31_74# vdd p w=6u l=0.6u
++ ad=0p pd=0u as=0p ps=0u 
+M5 a_34_4# a_22_6# vdd vdd p w=6u l=0.6u
++ ad=0p pd=0u as=0p ps=0u 
+M6 a_61_74# a_34_4# vdd vdd p w=6u l=0.6u
++ ad=0p pd=0u as=0p ps=0u 
+M7 a_66_6# a_2_6# a_61_74# vdd p w=6u l=0.6u
++ ad=0p pd=0u as=0p ps=0u 
+M8 a_76_84# clk a_66_6# vdd p w=3u l=0.6u
++ ad=0p pd=0u as=0p ps=0u 
+M9 vdd q a_76_84# vdd p w=3u l=0.6u
++ ad=0p pd=0u as=0p ps=0u 
+M10 gnd clk a_2_6# gnd n w=6u l=0.6u
++ ad=0p pd=0u as=0p ps=0u 
+M11 q a_66_6# vdd vdd p w=12u l=0.6u
++ ad=0p pd=0u as=0p ps=0u 
+M12 a_17_6# d gnd gnd n w=3u l=0.6u
++ ad=0p pd=0u as=0p ps=0u 
+M13 a_22_6# a_2_6# a_17_6# gnd n w=3u l=0.6u
++ ad=0p pd=0u as=0p ps=0u 
+M14 a_31_6# clk a_22_6# gnd n w=3u l=0.6u
++ ad=0p pd=0u as=0p ps=0u 
+M15 gnd a_34_4# a_31_6# gnd n w=3u l=0.6u
++ ad=0p pd=0u as=0p ps=0u 
+M16 a_34_4# a_22_6# gnd gnd n w=3u l=0.6u
++ ad=0p pd=0u as=0p ps=0u 
+M17 a_61_6# a_34_4# gnd gnd n w=3u l=0.6u
++ ad=0p pd=0u as=0p ps=0u 
+M18 a_66_6# clk a_61_6# gnd n w=3u l=0.6u
++ ad=0p pd=0u as=0p ps=0u 
+M19 a_76_6# a_2_6# a_66_6# gnd n w=3u l=0.6u
++ ad=0p pd=0u as=0p ps=0u 
+M20 gnd q a_76_6# gnd n w=3u l=0.6u
++ ad=0p pd=0u as=0p ps=0u 
+M21 q a_66_6# gnd gnd n w=6u l=0.6u
++ ad=0p pd=0u as=0p ps=0u 
+.ends dff

technology/scn3me_subm/tech/tech.py

@@ -238,6 +238,11 @@ spice["msflop_hold"] = 1         # DFF hold time in ps
 spice["msflop_delay"] = 20.5     # DFF Clk-to-q delay in ps
 spice["msflop_slew"] = 13.1      # DFF output slew in ps w/ no load
 spice["msflop_in_cap"] = 9.8242  # Input capacitance of ms_flop (Din) [Femto-farad]
+spice["dff_setup"] = 9        # DFF setup time in ps
+spice["dff_hold"] = 1         # DFF hold time in ps
+spice["dff_delay"] = 20.5     # DFF Clk-to-q delay in ps
+spice["dff_slew"] = 13.1      # DFF output slew in ps w/ no load
+spice["dff_in_cap"] = 9.8242  # Input capacitance of ms_flop (Din) [Femto-farad]
 
 
 ###################################################