From 066d00f44b13e91b9d169ec1952059c691e75dd9 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Fri, 1 Sep 2023 02:02:41 -0700 Subject: [PATCH] increase power ring crba width for drc --- compiler/modules/capped_replica_bitcell_array.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/capped_replica_bitcell_array.py b/compiler/modules/capped_replica_bitcell_array.py index db7a1547..83c4e109 100644 --- a/compiler/modules/capped_replica_bitcell_array.py +++ b/compiler/modules/capped_replica_bitcell_array.py @@ -223,7 +223,7 @@ class capped_replica_bitcell_array(bitcell_base_array): def route_power_ring(self, v_layer, h_layer): self.bbox = (vector(0,0), vector(self.capped_rba_width, self.capped_rba_height)) - self.supply_rail_width = drc["minwidth_m1"] + self.supply_rail_width = drc["minwidth_m3"] self.supply_rail_pitch = 6 * self.supply_rail_width self.add_power_ring(v_layer=v_layer, h_layer=h_layer)