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single port rba passing lvs

This commit is contained in:
Jesse Cirimelli-Low 2022-03-07 13:45:50 -08:00
parent 038acd1568
commit 0667a93d53
2 changed files with 45 additions and 3 deletions
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46
technology/sky130/modules/sky130_col_cap_array.py
View File

@ -89,10 +89,10 @@ class sky130_col_cap_array(sky130_bitcell_base_array):
elif col % 4 == 2: elif col % 4 == 2:
row_layout.append(self.colend1) row_layout.append(self.colend1)
self.cell_inst[col]=self.add_inst(name=name, mod=self.colend1) self.cell_inst[col]=self.add_inst(name=name, mod=self.colend1)
pins.append("fake_bl_{}".format(bitline)) pins.append("fake_br_{}".format(bitline))
pins.append("vdd") pins.append("vdd")
pins.append("gnd") pins.append("gnd")
pins.append("fake_br_{}".format(bitline)) pins.append("fake_bl_{}".format(bitline))
pins.append("gate") pins.append("gate")
bitline += 1 bitline += 1
elif col % 4 ==3: elif col % 4 ==3:
@ -170,6 +170,48 @@ class sky130_col_cap_array(sky130_bitcell_base_array):
offset=inst.lr(), offset=inst.lr(),
width=pin.width(), width=pin.width(),
height=pin.height()) height=pin.height())
for col in range(len(self.insts)):
inst = self.insts[col]
if col % 4 == 0:
pin = self.cell_inst[col].get_pin("bl")
text = "fake_bl_{}".format(int(col/2))
self.add_layout_pin(text=text,
layer=pin.layer,
offset=pin.ll().scale(1, 0),
width=pin.width(),
height=pin.height())
pin = self.cell_inst[col].get_pin("br")
text = "fake_br_{}".format(int(col/2))
self.add_layout_pin(text=text,
layer=pin.layer,
offset=pin.ll().scale(1, 0),
width=pin.width(),
height=pin.height())
elif col % 4 == 2:
pin = self.cell_inst[col].get_pin("bl")
text = "fake_br_{}".format(int(col/2))
self.add_layout_pin(text=text,
layer=pin.layer,
offset=pin.ll().scale(1, 0),
width=pin.width(),
height=pin.height())
pin = self.cell_inst[col].get_pin("br")
text = "fake_bl_{}".format(int(col/2))
self.add_layout_pin(text=text,
layer=pin.layer,
offset=pin.ll().scale(1, 0),
width=pin.width(),
height=pin.height())
return return
def add_supply_pins(self): def add_supply_pins(self):

2
technology/sky130/modules/sky130_replica_column.py
View File

@ -214,7 +214,7 @@ class sky130_replica_column(sky130_bitcell_base_array):
for port in self.all_ports: for port in self.all_ports:
for row in range(row_range_min, row_range_max): for row in range(row_range_min, row_range_max):
wl_pin = self.cell_inst[row].get_pin(self.cell.get_wl_name(port)) wl_pin = self.cell_inst[row].get_pin(self.cell.get_wl_name(port))
self.add_layout_pin(text="wl_{0}_{1}".format(port, row), self.add_layout_pin(text="wl_{0}_{1}".format(port, row_range_max-row),
layer=wl_pin.layer, layer=wl_pin.layer,
offset=wl_pin.ll().scale(0, 1), offset=wl_pin.ll().scale(0, 1),
width=self.width, width=self.width,