Split control logic into different tests to avoid factory errors.

2026-09-07 03:20:39 +02:00 · 2019-06-25 14:55:28 -07:00
parent 2b07db33c8
commit 04ce3d5f45
4 changed files with 62 additions and 41 deletions
@@ -54,7 +54,6 @@ class replica_pbitcell(design.design):
        
    def add_modules(self):
        self.prbc = factory.create(module_type="pbitcell",replica_bitcell=True)
-        debug.info(1,"rbl bitcell name={}".format(self.prbc.name))
        self.add_mod(self.prbc)
        
        self.height = self.prbc.height