diff --git a/compiler/bitcells/replica_pbitcell.py b/compiler/bitcells/replica_pbitcell.py
index d39d361a..30898d82 100644
--- a/compiler/bitcells/replica_pbitcell.py
+++ b/compiler/bitcells/replica_pbitcell.py
@@ -54,7 +54,6 @@ class replica_pbitcell(design.design):
         
     def add_modules(self):
         self.prbc = factory.create(module_type="pbitcell",replica_bitcell=True)
-        debug.info(1,"rbl bitcell name={}".format(self.prbc.name))
         self.add_mod(self.prbc)
         
         self.height = self.prbc.height
diff --git a/compiler/sram_factory.py b/compiler/sram_factory.py
index f53a72d5..0b079780 100644
--- a/compiler/sram_factory.py
+++ b/compiler/sram_factory.py
@@ -65,8 +65,6 @@ class sram_factory:
             # Must have the same dictionary exactly (conservative)
             if obj_kwargs == kwargs:
                 #debug.info(0, "Existing module: type={0} name={1} kwargs={2}".format(module_type, obj_item.name, str(kwargs)))
-                if module_type == 'bitcell_array':
-                    debug.info(1,'Returning existing mod!')
                 return obj_item
             #else:
             #    print("obj",obj_kwargs)
diff --git a/compiler/tests/16_control_logic_multiport_test.py b/compiler/tests/16_control_logic_multiport_test.py
new file mode 100755
index 00000000..66c34d24
--- /dev/null
+++ b/compiler/tests/16_control_logic_multiport_test.py
@@ -0,0 +1,59 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+#Copyright (c) 2016-2019 Regents of the University of California and The Board
+#of Regents for the Oklahoma Agricultural and Mechanical College
+#(acting for and on behalf of Oklahoma State University)
+#All rights reserved.
+#
+"""
+Run a regression test on a control_logic
+"""
+
+import unittest
+from testutils import header,openram_test
+import sys,os
+sys.path.append(os.path.join(sys.path[0],".."))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class control_logic_test(openram_test):
+
+    def runTest(self):
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
+        import control_logic
+        import tech
+
+        # check control logic for multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.replica_bitcell = "replica_pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_w_ports = 1
+        OPTS.num_r_ports = 1
+
+        debug.info(1, "Testing sample for control_logic for multiport, only write control logic")
+        a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="rw")
+        self.local_check(a)
+        
+        # OPTS.num_rw_ports = 0
+        # OPTS.num_w_ports = 1
+        debug.info(1, "Testing sample for control_logic for multiport, only write control logic")
+        a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="w")
+        self.local_check(a)
+        
+        # OPTS.num_w_ports = 0
+        # OPTS.num_r_ports = 1
+        debug.info(1, "Testing sample for control_logic for multiport, only read control logic")
+        a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="r")
+        self.local_check(a)
+
+        globals.end_openram()
+        
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main()
diff --git a/compiler/tests/16_control_logic_test.py b/compiler/tests/16_control_logic_test.py
index 78866d7b..21409132 100755
--- a/compiler/tests/16_control_logic_test.py
+++ b/compiler/tests/16_control_logic_test.py
@@ -26,45 +26,10 @@ class control_logic_test(openram_test):
         import control_logic
         import tech
 
-        # # check control logic for single port
-        # debug.info(1, "Testing sample for control_logic")
-        # a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32)
-        # self.local_check(a)
-        
-        # check control logic for multi-port
-        OPTS.bitcell = "pbitcell"
-        OPTS.replica_bitcell = "replica_pbitcell"
-        #OPTS.num_rw_ports = 1
-        OPTS.num_rw_ports = 0
-        OPTS.num_w_ports = 0
-        OPTS.num_r_ports = 0
-        
-        # debug.info(1, "Testing sample for control_logic for multiport")
-        # a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8)
-        # self.local_check(a)
-        
-        # # Check port specific control logic
-        # OPTS.num_rw_ports = 1
-        # OPTS.num_w_ports = 0
-        # OPTS.num_r_ports = 0
-
-        # debug.info(1, "Testing sample for control_logic for multiport, only write control logic")
-        # a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="rw")
-        # self.local_check(a)
-        
-        # OPTS.num_rw_ports = 0
-        # OPTS.num_w_ports = 1
-        # debug.info(1, "Testing sample for control_logic for multiport, only write control logic")
-        # a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="w")
-        # self.local_check(a)
-        
-        OPTS.num_w_ports = 0
-        OPTS.num_r_ports = 1
-        debug.info(1, "Testing sample for control_logic for multiport, only read control logic")
-        a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="r")
+        # check control logic for single port
+        debug.info(1, "Testing sample for control_logic")
+        a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32)
         self.local_check(a)
-
-        globals.end_openram()
         
 # run the test from the command line
 if __name__ == "__main__":