Rework macros to run ROM tests too.

macros/sram_configs/example_config_1rw_1r_scn4m_subm.py

@@ -0,0 +1,23 @@
+word_size = 2
+num_words = 16
+
+num_rw_ports = 1
+num_r_ports = 1
+num_w_ports = 0
+
+tech_name = "scn4m_subm"
+nominal_corner_only = False
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]
+
+route_supplies = True
+check_lvsdrc = True
+
+output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
+                                                      num_r_ports,
+                                                      num_w_ports,
+                                                      word_size,
+                                                      num_words,
+                                                      tech_name)
+output_path = "macro/{}".format(output_name)

macros/sram_configs/example_config_1rw_1w_scn4m_subm.py

@@ -0,0 +1,24 @@
+word_size = 4
+num_words = 16
+write_size = 2
+
+num_rw_ports = 1
+num_r_ports = 0
+num_w_ports = 1
+
+tech_name = "scn4m_subm"
+nominal_corner_only = False
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]
+
+route_supplies = False
+check_lvsdrc = True
+
+output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
+                                                      num_r_ports,
+                                                      num_w_ports,
+                                                      word_size,
+                                                      num_words,
+                                                      tech_name)
+output_path = "macro/{}".format(output_name)

macros/sram_configs/example_config_1rw_2mux_scn4m_subm.py

@@ -0,0 +1,24 @@
+word_size = 4
+num_words = 64
+words_per_row = 2
+
+num_rw_ports = 1
+num_r_ports = 0
+num_w_ports = 0
+
+tech_name = "scn4m_subm"
+nominal_corner_only = False
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]
+
+# route_supplies = True
+check_lvsdrc = True
+
+output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
+                                                      num_r_ports,
+                                                      num_w_ports,
+                                                      word_size,
+                                                      num_words,
+                                                      tech_name)
+output_path = "macro/{}".format(output_name)

macros/sram_configs/example_config_1w_1r_scn4m_subm.py

@@ -0,0 +1,24 @@
+word_size = 2
+num_words = 16
+
+num_rw_ports = 0
+num_r_ports = 1
+num_w_ports = 1
+
+tech_name = "scn4m_subm"
+nominal_corner_only = False
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]
+
+route_supplies = True
+check_lvsdrc = True
+
+output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
+                                                      num_r_ports,
+                                                      num_w_ports,
+                                                      word_size,
+                                                      num_words,
+                                                      tech_name)
+output_path = "macro/{}".format(output_name)
+

macros/sram_configs/example_config_2rw_scn4m_subm.py

@@ -0,0 +1,24 @@
+word_size = 2
+num_words = 16
+
+num_rw_ports = 2
+num_r_ports = 0
+num_w_ports = 0
+
+tech_name = "scn4m_subm"
+nominal_corner_only = False
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]
+
+route_supplies = False
+check_lvsdrc = True
+
+output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
+                                                      num_r_ports,
+                                                      num_w_ports,
+                                                      word_size,
+                                                      num_words,
+                                                      tech_name)
+output_path = "macro/{}".format(output_name)
+

macros/sram_configs/example_config_big_scn4m_subm.py

@@ -0,0 +1,22 @@
+word_size = 32
+num_words = 128
+
+num_rw_ports = 1
+num_r_ports = 0
+num_w_ports = 0
+
+
+tech_name = "scn4m_subm"
+nominal_corner_only = False
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]
+
+output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
+                                                      num_r_ports,
+                                                      num_w_ports,
+                                                      word_size,
+                                                      num_words,
+                                                      tech_name)
+output_path = "macro/{}".format(output_name)
+

macros/sram_configs/example_config_freepdk45.py

@@ -0,0 +1,28 @@
+word_size = 2
+num_words = 16
+
+num_rw_ports = 1
+num_r_ports = 0
+num_w_ports = 0
+
+
+tech_name = "freepdk45"
+nominal_corner_only = False
+process_corners = ["TT"]
+supply_voltages = [1.0]
+temperatures = [25]
+
+route_supplies = False
+check_lvsdrc = True
+# nominal_corner_only = True
+load_scales = [0.5, 1, 4]
+slew_scales = [0.5, 1]
+
+output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
+                                                      num_r_ports,
+                                                      num_w_ports,
+                                                      word_size,
+                                                      num_words,
+                                                      tech_name)
+output_path = "macro/{}".format(output_name)
+

macros/sram_configs/example_config_giant_scn4m_subm.py

@@ -0,0 +1,21 @@
+word_size = 64
+num_words = 1024
+
+num_rw_ports = 1
+num_r_ports = 0
+num_w_ports = 0
+
+
+tech_name = "scn4m_subm"
+nominal_corner_only = False
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]
+
+output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
+                                                      num_r_ports,
+                                                      num_w_ports,
+                                                      word_size,
+                                                      num_words,
+                                                      tech_name)
+output_path = "macro/{}".format(output_name)

macros/sram_configs/example_config_medium_scn4m_subm.py

@@ -0,0 +1,21 @@
+word_size = 16
+num_words = 256
+
+num_rw_ports = 1
+num_r_ports = 0
+num_w_ports = 0
+
+tech_name = "scn4m_subm"
+nominal_corner_only = False
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]
+
+output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
+                                                      num_r_ports,
+                                                      num_w_ports,
+                                                      word_size,
+                                                      num_words,
+                                                      tech_name)
+output_path = "macro/{}".format(output_name)
+

macros/sram_configs/example_config_scn4m_subm.py

@@ -0,0 +1,24 @@
+word_size = 2
+num_words = 16
+
+num_rw_ports = 1
+num_r_ports = 0
+num_w_ports = 0
+
+tech_name = "scn4m_subm"
+nominal_corner_only = False
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]
+
+route_supplies = "side"
+check_lvsdrc = True
+
+output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
+                                                      num_r_ports,
+                                                      num_w_ports,
+                                                      word_size,
+                                                      num_words,
+                                                      tech_name)
+output_path = "macro/{}".format(output_name)
+

macros/sram_configs/freepdk45_sram_1rw1r_32x2048_8.py

@@ -0,0 +1,26 @@
+word_size = 32
+num_words = 2048
+write_size = 8
+
+local_array_size = 32
+
+num_rw_ports = 1
+num_r_ports = 1
+num_w_ports = 0
+
+tech_name = "freepdk45"
+nominal_corner_only = True
+
+route_supplies = False
+check_lvsdrc = False
+perimeter_pins = False
+#netlist_only = True
+#analytical_delay = False
+
+output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
+                                                      num_r_ports,
+                                                      num_w_ports,
+                                                      word_size,
+                                                      num_words,
+                                                      tech_name)
+output_path = "macro/{}".format(output_name)

macros/sram_configs/scn4m_subm_sram_16kbyte_1rw1r_32x4096_8.py

@@ -0,0 +1,25 @@
+word_size = 32
+num_words = 4096
+write_size = 8
+
+local_array_size = 32
+
+num_rw_ports = 1
+num_r_ports = 1
+num_w_ports = 0
+
+tech_name = "scn4m_subm"
+nominal_corner_only = True
+
+route_supplies = False
+check_lvsdrc = False
+perimeter_pins = False
+#netlist_only = True
+#analytical_delay = False
+output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
+                                                      num_r_ports,
+                                                      num_w_ports,
+                                                      word_size,
+                                                      num_words,
+                                                      tech_name)
+output_path = "macro/{}".format(output_name)

macros/sram_configs/scn4m_subm_sram_1kbyte_1rw1r_32x256_8.py

@@ -0,0 +1,23 @@
+word_size = 32
+num_words = 256
+write_size = 8
+
+num_rw_ports = 1
+num_r_ports = 1
+num_w_ports = 0
+
+tech_name = "scn4m_subm"
+nominal_corner_only = True
+
+route_supplies = True
+check_lvsdrc = True
+perimeter_pins = False
+#netlist_only = True
+#analytical_delay = False
+output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
+                                                      num_r_ports,
+                                                      num_w_ports,
+                                                      word_size,
+                                                      num_words,
+                                                      tech_name)
+output_path = "macro/{}".format(output_name)

macros/sram_configs/scn4m_subm_sram_2kbyte_1rw1r_32x512_8.py

@@ -0,0 +1,23 @@
+word_size = 32
+num_words = 512
+write_size = 8
+
+num_rw_ports = 1
+num_r_ports = 1
+num_w_ports = 0
+
+tech_name = "scn4m_subm"
+nominal_corner_only = True
+
+route_supplies = True
+check_lvsdrc = True
+perimeter_pins = True
+#netlist_only = True
+#analytical_delay = False
+output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
+                                                      num_r_ports,
+                                                      num_w_ports,
+                                                      word_size,
+                                                      num_words,
+                                                      tech_name)
+output_path = "macro/{}".format(output_name)

macros/sram_configs/scn4m_subm_sram_32kbyte_1rw1r_2x32x4096_8.py

@@ -0,0 +1,26 @@
+num_banks=2
+word_size = 32
+num_words = 8192
+write_size = 8
+
+local_array_size = 32
+
+num_rw_ports = 1
+num_r_ports = 1
+num_w_ports = 0
+
+tech_name = "scn4m_subm"
+nominal_corner_only = True
+
+route_supplies = False
+check_lvsdrc = False
+perimeter_pins = False
+#netlist_only = True
+#analytical_delay = False
+output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
+                                                      num_r_ports,
+                                                      num_w_ports,
+                                                      word_size,
+                                                      num_words,
+                                                      tech_name)
+output_path = "macro/{}".format(output_name)

macros/sram_configs/scn4m_subm_sram_4kbyte_1rw1r_32x1024_8.py

@@ -0,0 +1,23 @@
+word_size = 32
+num_words = 1024
+write_size = 8
+
+num_rw_ports = 1
+num_r_ports = 1
+num_w_ports = 0
+
+tech_name = "scn4m_subm"
+nominal_corner_only = True
+
+route_supplies = True
+check_lvsdrc = True
+perimeter_pins = True
+#netlist_only = True
+#analytical_delay = False
+output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
+                                                      num_r_ports,
+                                                      num_w_ports,
+                                                      word_size,
+                                                      num_words,
+                                                      tech_name)
+output_path = "macro/{}".format(output_name)

macros/sram_configs/scn4m_subm_sram_8kbyte_1rw1r_32x2048_8.py

@@ -0,0 +1,25 @@
+word_size = 32
+num_words = 2048
+write_size = 8
+
+local_array_size = 32
+
+num_rw_ports = 1
+num_r_ports = 1
+num_w_ports = 0
+
+tech_name = "scn4m_subm"
+nominal_corner_only = True
+
+route_supplies = "tree"
+check_lvsdrc = True
+perimeter_pins = False
+#netlist_only = True
+#analytical_delay = False
+output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
+                                                      num_r_ports,
+                                                      num_w_ports,
+                                                      word_size,
+                                                      num_words,
+                                                      tech_name)
+output_path = "macro/{}".format(output_name)

macros/sram_configs/sky130_sram_1kbyte_1r1w_8x1024_8.py

@@ -0,0 +1,20 @@
+"""
+Pseudo-dual port (independent read and write ports), 8bit word, 1 kbyte SRAM.
+
+Useful as a byte FIFO between two devices (the reader and the writer).
+"""
+word_size = 8 # Bits
+num_words = 1024
+human_byte_size = "{:.0f}kbytes".format((word_size * num_words)/1024/8)
+
+# Allow byte writes
+write_size = 8 # Bits
+
+# Dual port
+num_rw_ports = 0
+num_r_ports = 1
+num_w_ports = 1
+ports_human = '1r1w'
+
+import os
+exec(open(os.path.join(os.path.dirname(__file__), 'sky130_sram_common.py')).read())

macros/sram_configs/sky130_sram_1kbyte_1rw1r_32x256_8.py

@@ -0,0 +1,21 @@
+"""
+Dual port (1 read/write + 1 read only) 1 kbytes SRAM with byte write.
+
+FIXME: What is this useful for?
+FIXME: Why would you want byte write on this?
+"""
+word_size = 32 # Bits
+num_words = 256
+human_byte_size = "{:.0f}kbytes".format((word_size * num_words)/1024/8)
+
+# Allow byte writes
+write_size = 8 # Bits
+
+# Dual port
+num_rw_ports = 1
+num_r_ports = 1
+num_w_ports = 0
+ports_human = '1rw1r'
+
+import os
+exec(open(os.path.join(os.path.dirname(__file__), 'sky130_sram_common.py')).read())

macros/sram_configs/sky130_sram_1kbyte_1rw1r_8x1024_8.py

@@ -0,0 +1,21 @@
+"""
+Dual port (1 read/write + 1 read only) 1 kbytes SRAM with byte write.
+
+FIXME: What is this useful for?
+FIXME: Why would you want byte write on this?
+"""
+word_size = 8 # Bits
+num_words = 1024
+human_byte_size = "{:.0f}kbytes".format((word_size * num_words)/1024/8)
+
+# Allow byte writes
+write_size = 8 # Bits
+
+# Dual port
+num_rw_ports = 1
+num_r_ports = 1
+num_w_ports = 0
+ports_human = '1rw1r'
+
+import os
+exec(open(os.path.join(os.path.dirname(__file__), 'sky130_sram_common.py')).read())

macros/sram_configs/sky130_sram_1kbyte_1rw_32x256_8.py

@@ -0,0 +1,21 @@
+"""
+Single port, 1 kbytes SRAM, with byte write, useful for RISC-V processor main
+memory.
+"""
+word_size = 32 # Bits
+num_words = 256
+human_byte_size = "{:.0f}kbytes".format((word_size * num_words)/1024/8)
+
+# Allow byte writes
+write_size = 8 # Bits
+
+# Single port
+num_rw_ports = 1
+num_r_ports = 0
+num_w_ports = 0
+num_spare_rows = 1
+num_spare_cols = 1
+ports_human = '1rw'
+
+import os
+exec(open(os.path.join(os.path.dirname(__file__), 'sky130_sram_common.py')).read())

macros/sram_configs/sky130_sram_1rw1r_tiny.py

@@ -0,0 +1,21 @@
+"""
+Dual port (1 read/write + 1 read only) 1 kbytes SRAM with byte write.
+
+FIXME: What is this useful for?
+FIXME: Why would you want byte write on this?
+"""
+word_size = 8 # Bits
+num_words = 16
+human_byte_size = "{:.0f}kbytes".format((word_size * num_words)/1024/8)
+
+# Allow byte writes
+write_size = 2 # Bits
+
+# Dual port
+num_rw_ports = 1
+num_r_ports = 1
+num_w_ports = 0
+ports_human = '1rw1r'
+
+import os
+exec(open(os.path.join(os.path.dirname(__file__), 'sky130_sram_common.py')).read())

macros/sram_configs/sky130_sram_1rw_tiny.py

@@ -0,0 +1,24 @@
+"""
+Dual port (1 read/write + 1 read only) 1 kbytes SRAM with byte write.
+
+FIXME: What is this useful for?
+FIXME: Why would you want byte write on this?
+"""
+word_size = 8 # Bits
+num_words = 16
+human_byte_size = "{:.0f}kbytes".format((word_size * num_words)/1024/8)
+
+# Allow byte writes
+write_size = 2 # Bits
+
+# Dual port
+num_rw_ports = 1
+num_r_ports = 0
+num_w_ports = 0
+ports_human = '1rw'
+
+num_spare_cols = 1
+num_spare_rows = 1
+
+import os
+exec(open(os.path.join(os.path.dirname(__file__), 'sky130_sram_common.py')).read())

macros/sram_configs/sky130_sram_2kbyte_1rw1r_32x512_8.py

@@ -0,0 +1,21 @@
+"""
+Dual port (1 read/write + 1 read only), 2 kbytes SRAM (with byte write).
+
+FIXME: What is this useful for?
+FIXME: Why would you want byte write on this?
+"""
+word_size = 32 # Bits
+num_words = 512
+human_byte_size = "{:.0f}kbytes".format((word_size * num_words)/1024/8)
+
+# Allow byte writes
+write_size = 8 # Bits
+
+# Dual port
+num_rw_ports = 1
+num_r_ports = 1
+num_w_ports = 0
+ports_human = '1rw1r'
+
+import os
+exec(open(os.path.join(os.path.dirname(__file__), 'sky130_sram_common.py')).read())

macros/sram_configs/sky130_sram_2kbyte_1rw_32x512_8.py

@@ -0,0 +1,21 @@
+"""
+Single port, 2 kbytes SRAM, with byte write, useful for RISC-V processor main
+memory.
+"""
+word_size = 32 # Bits
+num_words = 512
+human_byte_size = "{:.0f}kbytes".format((word_size * num_words)/1024/8)
+
+# Allow byte writes
+write_size = 8 # Bits
+
+# Single port
+num_rw_ports = 1
+num_r_ports = 0
+num_w_ports = 0
+num_spare_rows = 1
+num_spare_cols = 1
+ports_human = '1rw'
+
+import os
+exec(open(os.path.join(os.path.dirname(__file__), 'sky130_sram_common.py')).read())

macros/sram_configs/sky130_sram_4kbyte_1rw1r_32x1024_8.py

@@ -0,0 +1,22 @@
+"""
+Dual port (1 read/write + 1 read only), 4 kbytes SRAM (with byte write).
+
+FIXME: What is this useful for?
+FIXME: Why would you want byte write on this?
+"""
+
+word_size = 32 # Bits
+num_words = 1024
+human_byte_size = "{:.0f}kbytes".format((word_size * num_words)/1024/8)
+
+# Allow byte writes
+write_size = 8 # Bits
+
+# Dual port
+num_rw_ports = 1
+num_r_ports = 1
+num_w_ports = 0
+ports_human = '1rw1r'
+
+import os
+exec(open(os.path.join(os.path.dirname(__file__), 'sky130_sram_common.py')).read())

macros/sram_configs/sky130_sram_4kbyte_1rw_32x1024_8.py

@@ -0,0 +1,22 @@
+"""
+Single port, 4 kbytes SRAM, with byte write, useful for RISC-V processor main
+memory.
+"""
+
+word_size = 32 # Bits
+num_words = 1024
+human_byte_size = "{:.0f}kbytes".format((word_size * num_words)/1024/8)
+
+# Allow byte writes
+write_size = 8 # Bits
+
+# Single port
+num_rw_ports = 1
+num_r_ports = 0
+num_w_ports = 0
+num_spare_rows = 1
+num_spare_cols = 1
+ports_human = '1rw'
+
+import os
+exec(open(os.path.join(os.path.dirname(__file__), 'sky130_sram_common.py')).read())

macros/sram_configs/sky130_sram_4kbyte_1rw_64x512_8.py

@@ -0,0 +1,21 @@
+"""
+Single port, 1 kbytes SRAM, with byte write, useful for RISC-V processor main
+memory.
+"""
+word_size = 64 # Bits
+num_words = 512
+human_byte_size = "{:.0f}kbytes".format((word_size * num_words)/1024/8)
+
+# Allow byte writes
+write_size = 8 # Bits
+
+# Single port
+num_rw_ports = 1
+num_r_ports = 0
+num_w_ports = 0
+num_spare_rows = 1
+num_spare_cols = 1
+ports_human = '1rw'
+
+import os
+exec(open(os.path.join(os.path.dirname(__file__), 'sky130_sram_common.py')).read())

macros/sram_configs/sky130_sram_common.py

@@ -0,0 +1,21 @@
+# Include with
+#   import os
+#   exec(open(os.path.join(os.path.dirname(__file__), 'sky130_sram_common.py')).read())
+
+
+tech_name = "sky130"
+nominal_corner_only = True
+
+# Local wordlines have issues with met3 power routing for now
+#local_array_size = 16
+
+route_supplies = "ring"
+#route_supplies = "left"
+check_lvsdrc = True
+uniquify = True
+#perimeter_pins = False
+#netlist_only = True
+#analytical_delay = False
+
+output_name = "{tech_name}_sram_{human_byte_size}_{ports_human}_{word_size}x{num_words}_{write_size}".format(**locals())
+output_path = "macro/{output_name}".format(**locals())