mirror of https://github.com/VLSIDA/OpenRAM.git
29 lines
768 B
Python
29 lines
768 B
Python
word_size = 2
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num_words = 16
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num_rw_ports = 1
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num_r_ports = 0
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num_w_ports = 0
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tech_name = "freepdk45"
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nominal_corner_only = False
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process_corners = ["TT"]
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supply_voltages = [1.0]
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temperatures = [25]
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route_supplies = False
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check_lvsdrc = True
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# nominal_corner_only = True
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load_scales = [0.5, 1, 4]
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slew_scales = [0.5, 1]
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output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
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num_r_ports,
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num_w_ports,
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word_size,
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num_words,
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tech_name)
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output_path = "macro/{}".format(output_name)
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