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Clean up custom cells

This commit is contained in:
mrg 2020-10-08 14:22:09 -07:00
parent 8a9bf2d4f0
commit 03e1b9c50d
5 changed files with 29 additions and 49 deletions
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9
compiler/custom/s8_bitcell.py
View File

@ -10,7 +10,7 @@ import utils
from tech import GDS, layer from tech import GDS, layer
from tech import cell_properties as props from tech import cell_properties as props
import bitcell_base import bitcell_base
from globals import OPTS
class s8_bitcell(bitcell_base.bitcell_base): class s8_bitcell(bitcell_base.bitcell_base):
""" """
@ -38,7 +38,6 @@ class s8_bitcell(bitcell_base.bitcell_base):
def __init__(self, version, name=""): def __init__(self, version, name=""):
# Ignore the name argument # Ignore the name argument
if version == "opt1": if version == "opt1":
self.name = "s8sram_cell_opt1" self.name = "s8sram_cell_opt1"
elif version == "opt1a": elif version == "opt1a":
@ -49,14 +48,12 @@ class s8_bitcell(bitcell_base.bitcell_base):
self.pin_map = utils.get_libcell_pins(self.pin_names, self.name, GDS["unit"]) self.pin_map = utils.get_libcell_pins(self.pin_names, self.name, GDS["unit"])
self.add_pin_types(self.type_list) self.add_pin_types(self.type_list)
self.nets_match = self.do_nets_exist(self.storage_nets) self.nets_match = self.do_nets_exist(self.storage_nets)
(self.width, self.height) = utils.get_libcell_size(self.name, (self.width, self.height) = utils.get_libcell_size(self.name,
GDS["unit"], GDS["unit"],
layer["mem"]) layer["mem"])
def get_all_wl_names(self): def get_all_wl_names(self):
""" Creates a list of all wordline pin names """ """ Creates a list of all wordline pin names """

14
compiler/custom/s8_col_end.py
View File

@ -9,16 +9,13 @@
import debug import debug
import design import design
import utils import utils
from globals import OPTS from tech import layer, GDS
from tech import parameter, drc, layer, GDS
class s8_col_end(design.design): class s8_col_end(design.design):
def __init__(self, version, name=""): def __init__(self, version, name=""):
super().__init__(name) super().__init__(name)
pin_names = []
type_list = []
if version == "colend": if version == "colend":
self.name = "s8sram16x16_colend" self.name = "s8sram16x16_colend"
@ -32,10 +29,9 @@ class s8_col_end(design.design):
debug.error("Invalid type for col_end", -1) debug.error("Invalid type for col_end", -1)
design.design.__init__(self, name=self.name) design.design.__init__(self, name=self.name)
(self.width, self.height) = utils.get_libcell_size(self.name, (self.width, self.height) = utils.get_libcell_size(self.name,
GDS["unit"], GDS["unit"],
layer["mem"], layer["mem"])
structure) # pin_map = utils.get_libcell_pins(pin_names, self.name, GDS["unit"])
pin_map = utils.get_libcell_pins(pin_names, self.name, GDS["unit"])

13
compiler/custom/s8_corner.py
View File

@ -9,16 +9,13 @@
import debug import debug
import design import design
import utils import utils
from globals import OPTS from tech import layer, GDS
from tech import parameter, drc, layer, GDS
class s8_corner(design.design): class s8_corner(design.design):
def __init__(self, location, name=""): def __init__(self, location, name=""):
super().__init__(name) super().__init__(name)
pin_names = []
type_list = []
if location == "ul": if location == "ul":
self.name = "s8sram16x16_corner" self.name = "s8sram16x16_corner"
@ -32,6 +29,6 @@ class s8_corner(design.design):
debug.error("Invalid s8_corner location", -1) debug.error("Invalid s8_corner location", -1)
design.design.__init__(self, name=self.name) design.design.__init__(self, name=self.name)
(self.width, self.height) = utils.get_libcell_size(self.name, (self.width, self.height) = utils.get_libcell_size(self.name,
GDS["unit"], GDS["unit"],
layer["mem"]) layer["mem"])
pin_map = utils.get_libcell_pins(pin_names, self.name, GDS["unit"]) # pin_map = utils.get_libcell_pins(pin_names, self.name, GDS["unit"])

13
compiler/custom/s8_internal.py
View File

@ -9,16 +9,13 @@
import debug import debug
import design import design
import utils import utils
from globals import OPTS from tech import layer, GDS
from tech import parameter, drc, layer, GDS
class s8_internal(design.design): class s8_internal(design.design):
def __init__(self, version, name=""): def __init__(self, version, name=""):
super().__init__(name) super().__init__(name)
pin_names = []
type_list = []
if version == "wlstrap": if version == "wlstrap":
self.name = "s8sram_wlstrap" self.name = "s8sram_wlstrap"
@ -30,6 +27,6 @@ class s8_internal(design.design):
debug.error("Invalid version", -1) debug.error("Invalid version", -1)
design.design.__init__(self, name=self.name) design.design.__init__(self, name=self.name)
(self.width, self.height) = utils.get_libcell_size(self.name, (self.width, self.height) = utils.get_libcell_size(self.name,
GDS["unit"], GDS["unit"],
layer["mem"]) layer["mem"])
pin_map = utils.get_libcell_pins(pin_names, self.name, GDS["unit"]) # pin_map = utils.get_libcell_pins(pin_names, self.name, GDS["unit"])

23
compiler/custom/s8_replica_bitcell.py
View File

@ -8,11 +8,11 @@
import design import design
import debug import debug
import utils import utils
from tech import GDS,layer,drc,parameter,cell_properties from tech import GDS, layer, drc, parameter, cell_properties
from tech import cell_properties as props from tech import cell_properties as props
from globals import OPTS from globals import OPTS
class replica_bitcell(design.design): class replica_bitcell(design.design):
""" """
A single bit cell (6T, 8T, etc.) A single bit cell (6T, 8T, etc.)
@ -32,16 +32,6 @@ class replica_bitcell(design.design):
type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
if not OPTS.netlist_only:
(self.width, self.height) = utils.get_libcell_size(self.name,
GDS["unit"],
layer["mem"],
"s8sram_cell\x00")
self.pin_map = utils.get_libcell_pins(self.pin_names, self.name, GDS["unit"])
else:
(width,height) = (0,0)
pin_map = []
def __init__(self, version, name=""): def __init__(self, version, name=""):
# Ignore the name argument # Ignore the name argument
@ -56,11 +46,14 @@ class replica_bitcell(design.design):
design.design.__init__(self, "replica_cell_6t") design.design.__init__(self, "replica_cell_6t")
debug.info(2, "Create replica bitcell object") debug.info(2, "Create replica bitcell object")
self.width = replica_bitcell.width self.pin_map = utils.get_libcell_pins(self.pin_names, self.name, GDS["unit"])
self.height = replica_bitcell.height
self.pin_map = replica_bitcell.pin_map
self.add_pin_types(self.type_list) self.add_pin_types(self.type_list)
(self.width, self.height) = utils.get_libcell_size(self.name,
GDS["unit"],
layer["mem"])
def get_stage_effort(self, load): def get_stage_effort(self, load):
parasitic_delay = 1 parasitic_delay = 1
size = 0.5 #This accounts for bitline being drained thought the access TX and internal node size = 0.5 #This accounts for bitline being drained thought the access TX and internal node