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Remove partial Verilog output

This commit is contained in:
mrg 2020-11-17 16:51:08 -08:00
parent baae28194b
commit 02c1fac3b8
1 changed files with 0 additions and 3 deletions
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3
compiler/base/verilog.py
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@ -220,9 +220,6 @@ class verilog:
self.vf.write(" dout{0} <= #(DELAY) mem[addr{0}_reg];\n".format(port)) self.vf.write(" dout{0} <= #(DELAY) mem[addr{0}_reg];\n".format(port))
self.vf.write(" end\n") self.vf.write(" end\n")
self.vf.write(" always @(csb{0})\n".format(port))
self.vf.write(" dout{0} = 0)\n".format(port))
def add_address_check(self, wport, rport): def add_address_check(self, wport, rport):
""" Output a warning if the two addresses match """ """ Output a warning if the two addresses match """
# If the rport is actually reading... and addresses match. # If the rport is actually reading... and addresses match.