From 02c1fac3b8829cd751f3555d8223cc840bedb9ce Mon Sep 17 00:00:00 2001
From: mrg <mrg@ucsc.edu>
Date: Tue, 17 Nov 2020 16:51:08 -0800
Subject: [PATCH] Remove partial Verilog output

---
 compiler/base/verilog.py | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/compiler/base/verilog.py b/compiler/base/verilog.py
index f5ef9107..9760d6a1 100644
--- a/compiler/base/verilog.py
+++ b/compiler/base/verilog.py
@@ -220,9 +220,6 @@ class verilog:
         self.vf.write("       dout{0} <= #(DELAY) mem[addr{0}_reg];\n".format(port))
         self.vf.write("  end\n")
 
-        self.vf.write("  always @(csb{0})\n".format(port))
-        self.vf.write("       dout{0} = 0)\n".format(port))
-
     def add_address_check(self, wport, rport):
         """ Output a warning if the two addresses match """
         # If the rport is actually reading... and addresses match.